Our Events

Learn to migrate designs from Ultrascale+ to Versal in this workshop. Explore key differences in architectures for seamless transitions. Register now!

In this workshop, you will learn the fundamentals of the DFX concept; development and deployment will be covered as well

In this workshop, you will learn how to use MATLAB and Simulink to model and simulate hardware architectures and algorithms. System deployment to Versal Adaptive SoC boards using automatic HDL and C code generation will be covered as well.

In this workshop, you will learn about the Model-Based Design workflow using Model Composer, how to setup the Simulink model using blocks from HDL library and do automatic code generation, how to import a Model Composer HDL design into a bigger system.

Learn about Vitis Model Composer and its HLS block set in the Xilinx toolbox. Develop production-quality IP implementations using high-level synthesis technology. Join our workshop now!

5G and 6G communication systems will employ mm-Wave frequencies. This has made the development of highly integrated antenna arrays and RF front ends a standard practice. Engineers need to integrate RF,...

This webinar demonstrates the deployment of a Wireless System on an RFSoC device using Model-Based Design with MATLAB and Simulink. The talk emphasizes the benefits of this approach including system-level modeling, automated code generation, earlier verification, and faster adaptation to specification changes.

In this webinar, you will learn about single- and multi-user MIMO in 5G NR, as well as common beamforming techniques and scenarios. We will cover different techniques to estimate the channel or channel...

Learn how to use HDL Coder optimization and design techniques to meet your target-specific speed and area goals. HDL Coder offers techniques that span from automatic to fully-controlled, and all of them allow for rapid exploration of implementation options. This webinar will explain these options and their associated benefits and tradeoffs, including verification considerations, and will discuss techniques specific to FPGA and ASIC targeting.