Zynq UltraScale+ MPSoC for the Hardware Designer

This course provides hardware designers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.

TechSource Systems Pte Ltd

Course
Highlights

The emphasis of this two days course is on:

  • Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • Reviewing the various power domains and their control structure
  • Illustrating the processing system (PS) and programmable logic
    (PL) connectivity
  • Utilizing QEMU to emulate hardware behavior
TechSource Systems Pte Ltd

Who Should
Attend

Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device.

TechSource Systems Pte Ltd

Course
Prerequisites

  • Suggested: Understanding of the Zynq-7000 architecture
  • Basic familiarity with embedded software development using C(to
    support testing of specific architectural elements)
TechSource Systems Pte Ltd

Course
Benefits

After completing this comprehensive training, you will have the necessary skills to:

  • Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • List the various power domains and how they are controlled
  • Describe the connectivity between the processing system (PS) and programmable logic (PL)
  • Utilize QEMU to emulate hardware behavior

Partners

TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Zynq UltraScale+ MPSoC for the Hardware Designer

Application Processing Unit: Overview

Objective: You will be able to:

  • Differentiate the APU from other processing entities within the PS
  • Enumerate the major components of the APU­
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Application Processing Unit: Cortex-A53 Processor

Objective: You will be able to:

  • Describe the major supporting features of the Arm® Cortex™-A53 processor in the Zynq® UltraScale+™ MPSoC and RFSoC devices

Application Processing Unit: Architecture Extensions

Objective: You will be able to:

  • Describe the purpose and behavior of the NEON coprocessor
  • Elaborate on the provided coprocessor support for the APU cores
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Application Processing Unit: 64-Bit Architecture Features

Objective: You will be able to:

  • Describe the execution states of the Cortex™-A53 processor
  • Explain the intricacies of virtual addressing on a 64-bit Arm® processor

Application Processing Unit: Exception Handling

Objective: You will be able to:

  • Describe the vector table for 64-bit and 32-bit execution states
  • Summarize the differences in exception handling between 64-bit and 32-bit execution states
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Cache Coherency

Objective: You will be able to:

  • Describe the three basic tactics for handling data coherency
  • Describe the hardware components that manage data coherency

Hypervisors: Introduction

Objective: You will be able to:

  • Describe the purpose and types of a hypervisor
  • Enumerate the capabilities of a generic hypervisor
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Virtualization Hardware Support

Objective: You will be able to:

  • Define the interaction between hardware and software with respect to the hypervisor
  • Describe how the hypervisor interacts with system resource

Real-Time Processing Unit: Introduction

Objective: You will be able to:

  • Explain the high-level features of the RPU
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Real-Time Processing Unit: L1 and L2 Caches

Objective: You will be able to:

  • Explain what it means to be a “level X” device
  • Describe the view of memory from the perspective of the RPU

Real-Time Processing Unit: Clocking, Power, and Reset

Objective: You will be able to:

  • Identify the source of the RPU’s clock
  • Enumerate the power states that the RPU cores can enter
  • Describe the reset architecture as it relates to the RPU
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Real-Time Processing Unit: TCM Architecture

Objective: You will be able to:

  • Explain what tightly coupled memory (TCM) is, what it is used for, and why it is important
  • Describe the TCM capabilities in the Zynq® UltraScale+™ MPSoC PS families and how the TCM changes based on the RPU mode

QEMU: Introduction

Objective: You will be able to:

  • Define QEMU
  • Identify the benefits of using QEMU for software development
  • Describe how QEMU supports the Zynq® UltraScale+™ MPSoC
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

QEMU: Application Development and Debugging

Objective: You will be able to:

  • Identify the role of QEMU in the application development flow
  • Run and debug an application using QEMU and the Vitis™ IDE
  • Boot a Linux image on QEMU and run a Linux application using the QEMU and PetaLinux tools

Booting: Boot and Configuration

Objective: You will be able to:

  • List the processing units and their sequence during boot
  • Describe the firmware components and their configuration run during boot
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Booting: Boot Image

Objective: You will be able to:

  • List the key components or partitions that make up a boot image
  • Describe the tool and files required to generate a boot image

First Stage Boot Loader

Objective: You will be able to:

  • Describe the purpose of an FSBL
  • Explain how to implement the FSBL in an SoC device
TechSource Systems Pte Ltd

Video: Introduction to Video Codec Units

Objective: You will be able to:

  • Explain the need for a codec
  • Describe what a video codec unit (VCU) is
  • List the basic components of a VCU
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Video: VCU Architecture

Objective: You will be able to:

  • Identify different Zynq® UltraScale+™ MPSoC devices that have the hardened VCU core
  • Describe the VCU encoder and decoder architectures and features in Zynq UltraScale+ MPSoC EV devices
  • Describe the operation of the VCU
  • Describe the details of the VCU IP core

System Protection: System Memory Management Unit

Objective: You will be able to:

  • Describe the purpose of the system memory management unit (SMMU)
  • Explain the differences between the MMU and the SMMU
  • Describe the architecture of the SMMU
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

System Protection: Peripheral Protection Unit

Objective: You will be able to:

  • Identify the areas that the Xilinx peripheral protection unit (PPU) can regulate
  • Enumerate the operations performed by the Xilinx PPU
  • Describe the error handling flow of the Xilinx PPU

System Protection: Memory Protection Unit

Objective: You will be able to:

  • Identify the elements protected by the Xilinx memory protection unit (MPU)
  • Enumerate the operations performed by the Xilinx MPU
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Clocks and Resets: Clocking

Objective: You will be able to:

  • Identify how clocks are generated and distributed
  • Describe how clock frequencies can be changed

Clocks and Resets: PS Resets

Objective: You will be able to:

  • Describe the reset structure for the Zynq® UltraScale+™ MPSoC/RFSoC devices
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

AXI: Introduction

Objective: You will be able to:

  • Describe how AXI fits into the AMBA protocol developed by Arm
  • Explain what AXI is and what it is not

AXI: Variations

Objective: You will be able to:

  • Describe the differences & similarities among the three primary AXI variations
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

AXI: Transactions

Objective: You will be able to:

  • Identify the different types of AXI transactions

Power Management: Introduction

Objective: You will be able to:

  • Describe the capabilities of the platform management unit
  • Describe from a high level the PMU’s role in power management
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Power Management: Hardware Architecture

Objective: You will be able to:

  • Identify the responsibilities of the platform management unit (PMU)
  • Explain what the PMU firmware does and how it interacts with the other processors in the system
  • Describe how the PMU firmware’s functionality can be extended

Power Management: PMU and the IPIs

Objective: You will be able to:

  • Describe how the PMU communicates with the other processors in the PS
  • Explain the purpose for the PMU’s input and output register set
  • Describe the behavior of the PMU when an IPI is received
TechSource Systems Pte Ltd
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