

TechSource Systems is MathWorks Authorised Reseller and Training Partner
Provides experienced system architects with the knowledge on how to best architect a Zynq® System on a Chip (SoC) device project.
This two-day training Provide experiences system architects with the knowledge on how to best architect a Zynq® System on a Chip (SoC) device project.
This course covers:
What’s New for 2020.1
System architects who are interested in architecting a system on a chip using the SoC.
After completing this comprehensive training, you will have the necessary skills to:
TechSource Systems is MathWorks Authorised Reseller and Training Partner
Objective: overview of the Zynq® SoC without much detail in any particular area. The stage will be set to enable deeper dives into the features and operations of the Zynq SoC in the following modules.
Objective: explores the individual components that comprise the APU. For the most part, the APU is explored in isolation from the rest of the PS and PL.
Objective: explores the Neon co-processor that is the companion to each Cortex™-A9 processor in the Zynq® SoC processor system (PS) located in the application processor unit (APU) module.
Objective: introduces the components that comprise the input/output peripheral (IOP) block of the Zynq® device processing system (PS).
Objective: introduces the low-speed peripherals in the Zynq® SoC.
Objective: explores the operation of the DMAC, including a lab that demonstrates its operation.
Objective: introduces the direct memory access controller.
Objective: describes how AXI fits into the AMBA® protocol developed by Arm.
Objective: Describes in detail the PS interconnect and how it affects PL architecture decisions.
Objective: introduces and explains the operation of the on-chip (OCM) memory and various memory controllers located in the processing system (PS).
Objective: explains the boot process of the PS and configuration of the PL. The device configuration unit (DEVCFG) and the on-chip analog-to-digital converter (XADC) are also introduced.
Objective: Focuses on Zynq device performance, including DDR access from the PL, DMA considerations, and power control and reduction techniques.
Objective: Discusses the use and configuration of the PS in a hardware design.
Objective: Explores the software side of the Zynq device.
Objective: Explores the software side of the Zynq device.
Objective: Describes Xilinx-provided reference design platforms, use cases, and third-party operating systems and tools for the Zynq SoC.