Zynq SoC System Architecture

Provides experienced system architects with the knowledge on how to best architect a Zynq® System on a Chip (SoC) device project.

TechSource Systems Pte Ltd

Course
Highlights

This two-day training Provide experiences system architects with the knowledge on how to best architect a Zynq® System on a Chip (SoC) device project.

This course covers:

  • Identifying the features and benefits of the Zynq SoC architecture
  • Describing the architecture of the Arm® Cortex™-A9 processor-based processing system (PS) and the connections to the programmable logic (PL)
  • Detailing the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupts, and memory controllers
  • Effectively accessing and using the PS DDR controller from PL user logic
  • Interfacing PL-to-PS connections efficiently
  • Employing best practice design techniques for implementing functions in the PS or PL

What’s New for 2020.1

  • All labs have been updated to the latest software versions
TechSource Systems Pte Ltd

Who Should
Attend

System architects who are interested in architecting a system on a chip using the SoC.

TechSource Systems Pte Ltd

Course
Prerequisites

  • Digital system architecture design experience
  • Basic understanding of microprocessor architecture
  • Basic understanding of C programming
  • Basic HDL modeling experience
TechSource Systems Pte Ltd

Course
Benefits

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the architecture and components that comprise the Zynq SoC processing system (PS)
  • Relate a user design goal to the function, benefit, and use of the Zynq SoC
  • Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals
  • Analyze the tradeoffs and advantages of performing a function in software versus PL

Partners

TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Course Outline

Zynq SoC Overview

Objective: overview of the Zynq® SoC without much detail in any particular area. The stage will be set to enable deeper dives into the features and operations of the Zynq SoC in the following modules.

  • Zynq-7000 SoC Block Diagram
  • Zynq-7000 Family Highlights
  • Zynq SoC Block Diagram – APU
  • Zynq SoC Block Diagram – IOP
  • Multiplexed I/O (MIO)
  • AXI Ports of the PS-PL Interface
  • PS Memory Resources
  • PL Clocking Sources
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Zynq SoC Application Processor Unit (APU)

Objective: explores the individual components that comprise the APU. For the most part, the APU is explored in isolation from the rest of the PS and PL.

  • The Application Processor Unit (APU)
  • Arm Cortex-A9 Processor Features
  • Making and annotating plots
  • Memory Management Unit
  • TrustZone
  • Processor Caches
  • Cache Coherency Between processors
  • Triple Time Counter (TTC)
  • Generic Interrupt Controller (GIC)

Zynq SoC Neon Co-Processor

Objective: explores the Neon co-processor that is the companion to each Cortex™-A9 processor in the Zynq® SoC processor system (PS) located in the application processor unit (APU) module.

  • Introduction to NEON and Vector Processing
  • NEON Advantages
  • Floating-Point Unit (VFP)
  • NEON and FPU Instruction Formats
  • How to Use the NEON Co-Processor
  • What is OpenMAX?
  • NEON Automatic Vectorizing
  • Intrinsics
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TechSource Systems Pte Ltd

Zynq SoC Processor Input/Output Peripherals

Objective: introduces the components that comprise the input/output peripheral (IOP) block of the Zynq® device processing system (PS).

  • Input/Output Peripherals
  • Connecting to IOP
  • Multiplexed I/O (MIO) Pinout
  • Configuration of PS I/O Peripherals Demonstration

PS Peripherals

Objective: introduces the low-speed peripherals in the Zynq® SoC.

  • Low-Speed: UART: Introduces the UART low-speed peripheral
  • Low-Speed: CAN: Introduces the CAN low-speed peripheral
  • Low-Speed: I2C: Introduces the I2C low-speed peripheral
  • Low-Speed:SD/SDIO: Introduces the SD/SDIO low-speed peripheral
  • Low-Speed: SPI: Introduces the SPI low-speed peripheral
  • Low-Speed: GPIO: Introduces the GPIO low-speed peripheral
  • High-Speed: USB: Introduces the USB high-speed peripheral
  • High-Speed: Gigabit Ethernet: Introduces the Gigabit Ethernet high-speed peripheral
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

DMA Controller (DMAC)

Objective: explores the operation of the DMAC, including a lab that demonstrates its operation.

  • Eight-Channel DMA Controller (DMAC)
  • DMA Controller (DMAC) Block Diagram
  • DMA Programming
  • DMAC Data Movement Control
  • Defining DMA
  • DMA Operation Example
  • Features of the Zynq SoC DMAC

DMA

Objective: introduces the direct memory access controller.

  • Introduction and Features: Introduces the direct memory access controller
  • Block Design and Interrupts: Introduces the DMA block design and the DMA interrupts
  • Read and Write: Introduces the concepts behind DMA reading and writing
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AXI

Objective: describes how AXI fits into the AMBA® protocol developed by Arm.

  • Introduction: Introduces the AXI protocol
  • Variations: Describes the differences and similarities among the three primary AXI variations
  • Transactions: Describes different types of AXI transactions
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TechSource Systems Pte Ltd

Zynq SoC PS-PL Interface

Objective: Describes in detail the PS interconnect and how it affects PL architecture decisions.

  • Interfacing to Programmable Logic
  • Clocks and Resets
  • Interrupts
  • Understanding the PS-PL Interconnect Tradeoffs
  • General-Purpose Master AXI Port Features
  • General-Purpose Slave AXI Port Features
  • Typical ACP Accelerator Interaction
  • What are the Differences Between Slave HPx, GPx, and ACP?

Zynq SoC Memory Resources

Objective: introduces and explains the operation of the on-chip (OCM) memory and various memory controllers located in the processing system (PS).

  • Zynq Architecture Memory Features
  • PS External Memories
  • On-Chip Memory (OCM)
  • Static Memory Controller (SMC)
  • Dynamic Memory Controller (DMC)
  • Linear Quad SPI Flash Controller (QSPI)
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Zynq SoC Booting

Objective: explains the boot process of the PS and configuration of the PL. The device configuration unit (DEVCFG) and the on-chip analog-to-digital converter (XADC) are also introduced.

  • Primary Boot Interfaces – Chosen via Bootstrap Pins
  • Device Configuration Unit (DEVCFG)
  • Secure/Non-Secure Boot
  • Standard Zynq SoC Boot Model – PS is Boot Master
  • Programmable Logic Configuration – DMA-Based Device Configuration Block
  • Boot and Configuration Time – QSPI

Meeting Performance Goals

Objective: Focuses on Zynq device performance, including DDR access from the PL, DMA considerations, and power control and reduction techniques.

  • Zynq SoC Task Implementation Decisions
  • Hardware and Software Partitioning
  • Bandwidth, Latencies, and Performance Speed in the Zynq SoC
  • Zynq Device Power Table
  • Running the PS at Lower Frequencies
  • Running on One CPU
  • PS PLL in Bypass Mode
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Zynq SoC Hardware Design

Objective: Discusses the use and configuration of the PS in a hardware design.

  • Embedded Hardware Design Tools
  • Programmable Logic System on a Chip
  • Customizing the Zynq SoC PS
  • Clock Generation in the PS
  • CPU Clock Generation
  • Clocking the PL
  • Basic Clock Generator Design

Zynq SoC Software Design

Objective: Explores the software side of the Zynq device.

  • Zynq SoC Linux Support
  • Standalone Library
  • Processing System (PS) Boot Configuration Handoff
  • FSBL Support
  • Bootgen Tool
  • Running and Debugging a Linux Application on the Zynq SoC
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TechSource Systems Pte Ltd

Debugging the Zynq SoC

Objective: Explores the software side of the Zynq device.

  • Debug Tools Enabled by Arm CoreSight Technology
  • Difference Between Debug and Development Boot Stages
  • Zynq SoC JTAG Usage
  • Vivado Logic Analyzer Components
  • Verification and Debugging
  • Vivado Logic Analyzer Cores and Capabilities
  • QEMU Emulation
  • Debugging on the Zynq SoC

Zynq SoC Tools and Reference Designs

Objective: Describes Xilinx-provided reference design platforms, use cases, and third-party operating systems and tools for the Zynq SoC.

  • Evaluation Boards
  • Reference Designs
  • Linux and Other Operating Systems
  • Third-Party Tools
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