VHDL & FPGA Design Expert

Sign up for this introductory course the learn the basics of FPGA and Xilinx Vivado tools to get started for your peojnect.

TechSource Systems Pte Ltd

Course
Highlights

‘VHDL & FPGA Design Expert’ training is a comprehensive training course that comprises of 2 course modules: Designing with VHDL and Designing FPGAs Using the Vivado Design Suite 1. Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.

Designing with VHDL (3-day) provides a thorough introduction to the VHDL language. The emphasis is on writing efficient hardware designs, performing high-level HDL simulations, employing structural, register transfer level (RTL), and behavioral coding styles, targeting Xilinx devices specifically and FPGA devices in general, utilizing best coding practices.

Designing FPGA Using the Vivado Design Suite 1 (2-day) offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.

The course provides experience with creating a Vivado Design Suite project with source files, simulating a design, performing pin assignments, applying basic timing constraints, synthesizing and implementing, debugging a design, generating and downloading a bitstream onto a demo board.

Hands-on Project (1-day) on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor.

TechSource Systems Pte Ltd

Who Should
Attend

Digital designers who are interested in FPGA design training and want to use VHDL effectively for modeling, design, and synthesis of digital designs and learn to use Xilinx FPGAs.

TechSource Systems Pte Ltd

Course
Prerequisites

Basic digital design knowledge.

TechSource Systems Pte Ltd

Course
Benefits

After completing this training, you will have the necessary skills to:

Designing with VHDL

  • Implement the VHDL portion of coding for synthesis
  • Identify the differences between behavioral and structural coding styles
  • Distinguish coding for synthesis versus coding for simulation
  • Use scalar and composite data types to represent information
  • Use concurrent and sequential control structure to regulate
    information flow
  • Implement common VHDL constructs (finite state machines
    [FSMs], RAM/ROM data structures)
  • Simulate a basic VHDL design
  • Write a VHDL testbench and identify simulation-only constructs
  • Identify and implement coding best practices
  • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
  • Create and manage designs within the Vivado Design Suite
    environment

FPGA Design Expert

  • Use the New Project Wizard to create a new Vivado IDE project
  • Describe the supported design flows of the Vivado IDE
  • Generate a DRC report to detect and fix design issues early in the flow
  • Use the Vivado IDE I/O Planning layout to perform pin assignments
  • Synthesize and implement the HDL design
  • Apply clock and I/O timing constraints and perform timing analysis
  • Describe the “baselining” process to gain timing closure on a
    design
  • Use the Schematic and Hierarchy viewers to analyze and
    cross-probe a design
  • Use the Vivado logic analyzer and debug cores to debug a design

Partners

TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Course Outline

Part 1: Designing with VHDL

TechSource Systems Pte Ltd

Introduction to VHDL

Objective: Discusses the history of the VHDL language and provides an overview of the different features of VHDL.

  • Describe the original intent of VHDL and how this intent has influenced the design of the language
  • Define key terms and concepts in relationship to VHDL
  • Describe the different coding styles that are available in VHDL

VHDL Design Units

Objective: Provides an overview of typical VHDL code, covering design units such as libraries, packages, entities, architectures, and configuration.

  • Describe the design units that are available in VHDL code
  • Define the library and packages and how they are declared
  • Explain entity and architecture syntax and declarations
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

VHDL Objects, Keywords, Identifiers

Objective: VHDL Objects, Keywords, Identifiers.

  • Use appropriate keywords in VHDL
  • Describe identifiers and the rules for writing identifiers
  • Comment a piece of VHDL code

Scalar Data Types

Objective: Covers both intrinsic and commonly used data types.

  • Use appropriate data types when declaring ports and signals
  • List legal values for std_logic data types
  • Create scalar data types
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Composite Data Types

Objective: Covers composite data types (arrays and records).

  • Describe what composite data types are
  • Create composite data types (array and record)
  • Declare one-dimensional and two-dimensional arrays

VHDL Operators

Objective: Reviews all VHDL operator types.

  • Analyze all the operators that are available in VHDL
  • Use these operators in VHDL code
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Concurrency in VHDL

Objective: Describes concurrent statements and how signals help in achieving concurrency.

  • Describe what a signal is and how it behaves in a concurrent use
  • Describe how to define a constant and how it behaves
  • Define the event and transaction
  • Define the concept of data cycles

Concurrent Assignments

Objective: Covers both conditional and unconditional assignments.

  • Define the types of concurrent statements
  • Use the generate statement in your code
  • Show how to make unconditional and conditional assignments
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Processes and Variables

Objective: Introduces sequential programming techniques for a concurrent language. Variables are also discussed.
Objective: Covers both conditional and unconditional assignments.

  • Describe what a process is and why it is beneficial
  • Explain the purpose and proper implementation of a process sensitivity list
  • Show how to define variables and compare and contrast them to signals

Conditional Statements in VHDL: if/else, case

Objective: Describes conditional statements such as if/else and case statements.

  • Enumerate control structures within a process
  • Use if/else and case statements in your code
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Sequential Looping Statements

Objective: Introduces the concept of looping in both the simulation and synthesis environments.

  • Describe the available looping structures in VHDL and where they can be used

Delays in VHDL: wait Statement

Objective: Describes conditional statements such as if/else and case statements.

  • Describe the delay types available in VHDL
  • Define the four types of the wait statement
  • List the key concepts for good coding style with respect to synchronous processes
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Introduction to the VHDL Testbench

Objective: Introduces the concept of the VHDL testbench to verify the functionality of a design.

  • Define a testbench
  • Write a simple testbench
  • Identify the basic components of a testbench

VHDL Assert Statements

Objective: Describes the concept of VHDL assertions.

  • Define a VHDL assertion and its syntax
  • Write an assert statement
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

VHDL Attributes

Objective: Describes attributes, both predefined and user defined.

  • Enumerate the three classes of “tic” attributes
  • Use signal attributes in VHDL code
  • Demonstrate how to locate and employ synthesis and implementation attributes

VHDL Subprograms

Objective: Covers the use of subprograms in verification and RTL code to model functional blocks.

  • Describe the use of subprograms in VHDL coding
  • Differentiate between functions and procedures
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

VHDL Functions

Objective: Describes functions, which are integral to reusable and
maintainable code.

  • Write functions in your VHDL code
  • Use function overloading in the code

VHDL Procedures

Objective: Describes procedures, common constructs that are also important for reusing and maintaining code.

  • Describe procedures and their syntax
  • Write procedures in your VHDL code
TechSource Systems Pte Ltd

VHDL Libraries and Packages

Objective: Demonstrates how libraries and packages are declared and used.

  • Enumerate the frequently used standard libraries and identify the relevant contents of each
  • Explain how to create packages and libraries
  • Describe the contents of a package and a library
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Interacting with Simulation

Objective: Describes how to interact with a simulation via text I/O.

  • Indicate the various points in the development flow appropriate for simulation
  • Explain the contents of the TextIO library (output capabilities only)

Finite State Machine Overview

Objective: Provides an overview of finite state machines, one of the more commonly used circuits.

  • Describe what a finite state machine is
  • Describe the basic VHDL considerations for a finite state machine
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Mealy Finite State Machine

Objective: Describes how to implement a Mealy state machine in which the output is dependent on both the current state and the inputs.

  • Describe what a Mealy finite state machine is

Moore Finite State Machine

Objective: Demonstrates how to implement a Moore state machine in which the output is dependent on the current state only.

  • Describe what a Moore finite state machine is
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

FSM Coding Guidelines

Objective: Describes the guidelines and recommendations for using one or more procedural blocks when coding a finite state machine.

  • Enumerate principle good programming practices when using state machines
  • List several mechanisms for implementing finite state machines

Vivado Simulator and Race Conditions in VHDL

Objective: Introduces the Vivado simulator simulation environment. Race conditions are also discussed.

  • Describe how the Vivado® simulator works
  • Using the Vivado simulator
  • Define race conditions in VHDL
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Writing a Good Testbench

Objective: Explores how time-agnostic, self-checking testbenches can be written and applied.

  • Describe how a self-checking testbench can be constructed
  • Illustrate proper annotation techniques

Targeting Xilinx FPGAs

Objective: Focuses on Xilinx-specific implementation and chip-level optimization.

  • Describe the challenges of using an HDL approach for FPGA designs
  • Identify the factors that directly affect FPGA timing and performance
  • Identify the trade-offs and guidelines for logic inference and instantiation
  • Describe typical synthesis compiler options and their benefits
  • List synthesis considerations unique to Xilinx FPGAs
TechSource Systems Pte Ltd

Part 2: FPGA Design Expert

TechSource Systems Pte Ltd

Introduction to FPGA Architecture, 3D ICs, SoCs, ACAPs

Objective: Overview of FPGA architecture, SSI technology, and SoC device architecture.

  • FPGA architecture
  • major building blocks of FPGAs
  • stacked silicon-based 3D IC devices
  • SoC devices
  • Describe Adaptive Compute Acceleration Platforms (ACAPs)

UltraFast Design Methodology: Board and Device Planning

Objective: Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.

  • UltraFastTM Design Methodology checklist to identify common mistakes and decision points throughout the design process
  • which FPGA device resources need particular attention in a design
  • importance of following a proper pin planning methodology
  • what power considerations you need to take into account when planning for the PCB design
  • Fix design issues earlier in the design flow
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

HDL Coding Techniques

Objective: Covers basic digital coding guidelines used in an FPGA design.

  • use of control signals (sets, resets, and clock enables) can impact your device utilization
  • Describe the benefits of following Xilinx recommendations on resets
  • difference between inference and instantiation
  • design coding to infer the dedicated hardware resources
  • Describe the recommended coding techniques

Introduction to Vivado Design Flows

Objective: Introduces the Vivado design flows: the project flow and non-project batch flow.

  • various design flows in the Vivado® Design Suite
  • RTL-to-bitstream design flow
  • supported use models in the Vivado Design Suite
  • system-level integration flows
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Vivado Design Suite Project-based Flow

Objective: Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design.

  • project mode use model in the Vivado® Design Suite
  • structure and files of a project
  • Vivado Design Suite project in project mode

Introduction to Vivado Reports

Objective: Generate and use Vivado timing reports to analyze failed timing paths.

  • different reports generated by the Vivado® IDE
  • timing reports and commands used by the Vivado IDE
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Behavioral Simulation

Objective: Describes the process of behavioral simulation and the simulation options available in the Vivado® IDE.

  • benefits of behavioral simulation
  • behavioral simulation on a design
  • functionality of a design

Xilinx Power Estimator Spreadsheet

Objective: Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.

  • estimate power consumption by using the Xilinx Power Estimator (XPE) spreadsheet
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Vivado Synthesis and Implementation

Objective: Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.

  • synthesis and implementation options and directives
  • Synthesize and implement an HDL design
  • programs that are available as part of the synthesis and implementation process

Vivado IP Flow

Objective: Customize IP, instantiate IP, and verify the hierarchy of your design IP.

  • managed IP flow in the Vivado® IDE
  • IP catalog from the project to customize and add IP to the design
  • usage of IP output files
  • synthesis options for IP
  • block design container feature in the Vivado IP integrator
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Vivado Design Suite I/O Pin Planning

Objective: Use the I/O Pin Planning layout to perform pin assignments in a design.

  • I/O planning project in the Vivado® IDE
  • Package Pins and I/O Ports windows in the Vivado IDE
  • I/O ports interactivity
  • relationship between I/O banks and the logic in your design

Introduction to Clock Constraints

Objective: Apply clock constraints and perform timing analysis.

  • what is a clock
  • appropriate clock constraints for your design
  • input jitter and clock latency
  • clocks present in the design
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Generated Clocks

Objective: Use the report clock networks report to determine if there are any generated clocks in a design.

  • generated clocks
  • automatically and manually generated clocks
  • relationship between a generated clock and the source clock

I/O Constraints and Virtual Clocks

Objective: Apply I/O constraints and perform timing analysis.

  • appropriate input and output delays for your design
  • virtual clocks for input and output delays in your design
  • timing reports that involve inputs and outputs
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Timing Constraints Wizard

Objective: Use the Timing Constraints Wizard to apply missing timing constraints in a design.

  • Timing Constraints Wizard to create timing constraints
  • completion of timing constraints using the Timing Constraints Wizard

Basics of Clock Gating and Static Timing Analysis

Objective: Describes the basics of clock gating and static timing analysis.

  • basics of clock gating
  • basics of static timing analysis
  • setup and hold slack
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Calculating Setup and Hold Timing

Objective: Reviews setup and hold timing calculations.

  • setup and hold slacks
  • input setup and hold analysis
  • output setup and hold analysis

Introduction to FPGA Configuration

Objective: Describes how FPGAs can be configured.

  • basic FPGA configuration process
  • purpose of each of the FPGA configuration pins
  • FPGA configuration files
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Introduction to the Vivado Logic Analyzer

Objective: Overview of the Vivado logic analyzer for debugging a design.

  • what is Vivado® Logic Analyzer (VLA), as well as the fundamental components that comprise the Vivado debug tool
  • benefits of the Vivado logic analyzer
  • basic probing flows to debug your design

Introduction to Triggering

Objective: Introduces the trigger capabilities of the Vivado logic analyzer.

  • trigger mechanism of the Vivado® logic analyzer
  • using the Run Trigger option
  • captured data using the waveform view
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Debug Cores

Objective: Understand how the debug hub core is used to connect debug cores in a design.

  • ILA core and its properties
  • VIO and IBERT core usage
  • what the debug core hub is and why it is used
  • debug core hub insertion and customization

Introduction to the Tcl Environment

Objective: Introduces Tcl (tool command language).

  • popular uses and benefits of using Tcl commands in an FPGA design development flow
  • how Tcl scripts can be executed from within the interactive environment
  • ways of running the Vivado® IDE with Tcl commands
  • access the help feature
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Tcl Syntax and Structure

Objective: Understand the Tcl syntax and structure.

  • basic syntax and language structure of Tcl
  • Running Tcl commands and scripts interactively and in a shell
  • Tcl command structure
  • substitutions made by the Tcl parser
  • comments and use the puts command
  • strings, brackets, and quoting

Using Tcl Commands in the Vivado Design Suite Project Flow

Objective: Explains what Tcl commands are executed in a Vivado Design Suite project flow.

  • contents of a basic Vivado® IDE script
  • basic Tcl commands in a project-based flow
  • Tcl script
TechSource Systems Pte Ltd

Hands-on-Project

FPGA Design Flow Hands-on practices.

TechSource Systems Pte Ltd
QUICK ENQUIRY