Designing with Verilog

This comprehensive course provides a thorough introduction to the Verilog language.

TechSource Systems Pte Ltd

Course
Highlights

Taught by FPGA designers, the course provides the essential MUST-KNOW knowledge required to pick up Verilog HDL quickly and its applications to digital hardware design. Training will be complemented with lab exercises targeting to a FPGA evaluation board.

TechSource Systems Pte Ltd

Who Should
Attend

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

TechSource Systems Pte Ltd

Course
Prerequisites

  • Basic digital design knowledge
TechSource Systems Pte Ltd

Course
Benefits

After completing this comprehensive training, you will have the
necessary skills to:

  • Write RTL Verilog code for synthesis
  • Write Verilog test fixtures for simulation
  • Create a finite state machine (FSM) by using Verilog
  • Target and optimize Xilinx FPGAs by using Verilog
  • Use enhanced Verilog file I/O capabilities
  • Run a timing simulation by using Xilinx Simprim libraries
  • Create and manage designs within the Vivado Design Suite environment
  • Download to the evaluation demo board

Partners

TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Course Outline

Introduction to Verilog

Objective: Discusses the history of the Verilog language and provides an overview of the different features of Verilog.

  • origin of the Verilog HDL
  • common “levels of abstraction” for hardware modeling
  • subsets of the Verilog syntax
  • basic guidelines for creating a hierarchical design structure
  • accesses components from the vendor-specific library and why instantiation may be preferable to inference
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Verilog Keywords and Identifiers

Objective: Discusses the data objects that are available in the Verilog language as well as keywords and identifiers.

  • keywords and identifiers found in the Verilog environment

Verilog Data Values and Number Representation

Objective: Covers what data values are in Verilog, as well as how to represent numbers in Verilog.

  • data values supported by Verilog
  • how numbers are represented in the Verilog environment
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Verilog Data Types

Objective: Covers the various data types in Verilog.

  • objects in the Verilog environment
  • correct Verilog data type throughout your source code

Verilog Buses and Arrays

Objective: Covers buses and arrays in Verilog.

  • what is data bus
  • Declare, assign to, and manipulate portions of a data bus
  • memory structure using arrays
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Verilog Modules and Ports

Objective: Describes both the syntax and hierarchy for a Verilog module, port declarations, and the difference between reg versus wire.

  • basic Verilog module description
  • module ports based on their intended usage
  • hierarchical structures in Verilog code

Verilog Operators

Objective: Shows the syntax for all Verilog operators.

  • types and classes of Verilog operators
  • common Verilog operators to model a variety of functions
  • arithmetic operators to perform standard arithmetic functions on signals and buses
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Continuous Assignment

Objective: Introduces the Verilog continuous assignment statement.

  • Model logic by using a Verilog assign statement
  • delay specifications on the logic

Gate-Level Modeling

Objective: Introduces gate-level modeling in Verilog.

  • design ingate-level modeling
  • gate delays to the logic primitives
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Procedural Assignment

Objective: Provides an introduction to procedural assignments in Verilog, including their usage and restrictions.

  • design using behavioral modeling
  • use of Verilog initial and always procedure blocks

Blocking and Non-Blocking Procedural Assignment

Objective: Introduces blocking and non-blocking assignment statements in Verilog.

  • blocking and non-blocking assignments
  • Use blocking and non-blocking statements appropriately in design
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Procedural Timing Control

Objective: Introduces the timing control methods that are used in procedural assignments.

  • time control in procedural blocks
  • different types of procedural timing control

Verilog Conditional Statements: if_else

Objective: Describes the if/else conditional statement.

  • if-else statements to produce optimal logic
  • important guidelines for effective default statements
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Verilog Conditional Statements: case

Objective: Describes the case conditional statement.

  • case statements to produce optimal logic
  • important guide lines while writing a case statement

Verilog Loop Statements

Objective: Introduces the different types of Verilog loop statements.

  • loop statements to control repeated execution of statements
  • different loop statements available in Verilog
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Introduction to the Verilog Testbench

Objective: Introduces the concept of the Verilog testbench.

  • concept and general application of a testbench
  • simulation only and synthesizable constructs
  • basic recommendations for effective design verification
  • necessary components for creating and executing a Verilog testbench
  • basic input stimulus and model input clocks

System Tasks

Objective: Provides a basic understanding of system tasks.

  • $display, $strobe, and $monitor for simulator tasks
  • Display simulation time in the desired format
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Verilog Subprograms

Objective: Covers the use of subprograms in verification and RTL code to model functional blocks.

  • use of subprograms in Verilog HDL coding
  • functions and tasks

Verilog Functions

Objective: Describes functions, which are integral to reusable and maintainable code.

  • Declare and use functions within Verilog code
  • types offunctions
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Verilog Tasks

Objective: Covers tasks in Verilog.

  • Declare and use tasks within Verilog code

Verilog Compiler Directives

Objective: Describes Verilog compiler directives.

  • compiler directives in Verilog HDL coding
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Verilog Parameters

Objective: Covers Verilog parameters and the local parameter concept.

  • what is a parameter
  • Declare the local parameter as appropriate
  • Update the value of a parameter

Verilog Generate Statements

Objective: Introduces the Verilog generate statement.

  • Verilog generate statement for repetitive or conditional logic implementation
  • different methods to create generate statements in your design
TechSource Systems Pte Ltd

Timing Checks

Objective: Covers the timing check statements in Verilog and talks about the specify block.

  • timing checks statements in design
  • the specify block
  • timing violations for design
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Finite State Machines

Objective: Provides an overview of finite state machines, one of the more commonly used circuits.

  • what is a finite state machine
  • basic Verilog considerations for FSM

Mealy Finite State Machine

Objective: Describes the Mealy FSM and how to code for it.

  • what is a Mealy finite state machine
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Moore Finite State Machine

Objective: Describes the Moore FSM and how to code for it.

  • what is a Moore finite state machine

FSM Coding Guidelines

Objective: Shows how to model an FSM of any complexity in Verilog and describes recommendations for performance and reliability.

  • implications of using one or more procedural blocks while coding for FSM
  • guidelines and recommendation presented in this module
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Avoiding Race Conditions in Verilog

Objective: Objective: Describe what a race condition is and provides steps to avoid this condition.

  • what is a race condition
  • types of race conditions
  • simulation event queue
  • guidelines to avoid race conditions

File I/O: Introduction

Objective: Covers using basic and enhanced Verilog file I/O capabilities for more robust design verification.

  • benefits of using Verilog file I/O during simulation
  • process for creating and opening files and controlling access
  • Verilog $readmemb or $readmemh during simulation
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

File I/O: Read Functions

Objective: Objective: Covers Verilog file I/O read capabilities.

  • enhanced Verilog file I/O read operations
  • $fgets and $fscanf functions during simulation

File I/O: Write Functions

Objective: Covers Verilog file I/O write capabilities.

  • enhanced Verilog file I/O write operations
  • when to use $fwrite and $fdisplay during simulation
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Targeting Xilinx FPGAs

Objective: Focuses on Xilinx-specific implementation and chip-level optimization.

  • challenges of using an HDL approach for FPGA designs
  • factors that directly affect FPGA timing and performance
  • trade-offs and guidelines for logic inference and instantiation
  • typical synthesis compiler options and their benefits
  • synthesis considerations unique to Xilinx FPGAs

User-Defined Primitives

Objective: Describes user-defined primitives (UDPs).

  • modeling technique to expand built-in primitives
  • UDPs to represent the circuit being modeled
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Programming Language Interface

Objective: Introduces the programming language interface (PLI) in Verilog.

  • what the programming language interface (PLI) is
  • benefits ofusing the PLI
  • PLI in the Verilog code to access C functions
QUICK ENQUIRY