TechSource Systems is MathWorks Authorised Reseller and Training Partner
This comprehensive course provides a thorough introduction to the Verilog language.
Taught by FPGA designers, the course provides the essential MUST-KNOW knowledge required to pick up Verilog HDL quickly and its applications to digital hardware design. Training will be complemented with lab exercises targeting to a FPGA evaluation board.
Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs
After completing this comprehensive training, you will have the
necessary skills to:
Objective: Discusses the history of the Verilog language and provides an overview of the different features of Verilog.
Objective: Discusses the data objects that are available in the Verilog language as well as keywords and identifiers.
Objective: Covers what data values are in Verilog, as well as how to represent numbers in Verilog.
Objective: Covers the various data types in Verilog.
Objective: Covers buses and arrays in Verilog.
Objective: Describes both the syntax and hierarchy for a Verilog module, port declarations, and the difference between reg versus wire.
Objective: Shows the syntax for all Verilog operators.
Objective: Introduces the Verilog continuous assignment statement.
Objective: Introduces gate-level modeling in Verilog.
Objective: Provides an introduction to procedural assignments in Verilog, including their usage and restrictions.
Objective: Introduces blocking and non-blocking assignment statements in Verilog.
Objective: Introduces the timing control methods that are used in procedural assignments.
Objective: Describes the if/else conditional statement.
Objective: Describes the case conditional statement.
Objective: Introduces the different types of Verilog loop statements.
Objective: Introduces the concept of the Verilog testbench.
Objective: Provides a basic understanding of system tasks.
Objective: Covers the use of subprograms in verification and RTL code to model functional blocks.
Objective: Describes functions, which are integral to reusable and maintainable code.
Objective: Covers tasks in Verilog.
Objective: Describes Verilog compiler directives.
Objective: Covers Verilog parameters and the local parameter concept.
Objective: Introduces the Verilog generate statement.
Objective: Covers the timing check statements in Verilog and talks about the specify block.
Objective: Provides an overview of finite state machines, one of the more commonly used circuits.
Objective: Describes the Mealy FSM and how to code for it.
Objective: Describes the Moore FSM and how to code for it.
Objective: Shows how to model an FSM of any complexity in Verilog and describes recommendations for performance and reliability.
Objective: Objective: Describe what a race condition is and provides steps to avoid this condition.
Objective: Covers using basic and enhanced Verilog file I/O capabilities for more robust design verification.
Objective: Objective: Covers Verilog file I/O read capabilities.
Objective: Covers Verilog file I/O write capabilities.
Objective: Focuses on Xilinx-specific implementation and chip-level optimization.
Objective: Describes user-defined primitives (UDPs).
Objective: Introduces the programming language interface (PLI) in Verilog.