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Verification with SystemVerilog
Introducdion of SystemVerilog constructs for Verification
Course
Highlights
This two-day course provides an introduction to SystemVerilog constructs for verification.
This course emphasis is on:
- Writing testbenches to verify a design under test (DUT) utilizing the constructs available in SystemVerilog
- Reviewing object-oriented modeling, data types, reusable tasks
and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI)
What’s New for 2021.1
- All labs have been updated to the latest software versions
Who Should
Attend
Hardware and verification engineers.
Course
Prerequisites
Experienced Verilog user or completion of the Designing with Verilog course
Course
Benefits
After completing this comprehensive training, you will have the necessary skills to:
- Describe the advantages and enhancements to SystemVerilog to support verification
- Define the new data types available in SystemVerilog
- Analyze and use the improvements to tasks and functions
- Discuss and use the various new verification building blocks available in SystemVerilog
- Describe object-oriented programming and create a class-based verification environment
- Explain the various methods for creating random data
- Create and utilize random data for generating stimulus to a DUT
- Identify how SystemVerilog enhances functional coverage for
simulation verification - Utilize assertions to quickly identify correct behavior in simulation
- Identify how the direct programming interface can be used with C/C++ in a verification environment
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Introduction to SystemVerilog
Objective: provides an introduction to the SystemVerilog language.
- Definition of SystemVerilog
- Motivation for SystemVerilog
- History and Formalization of SystemVerilog
- FPGAs and SystemVerilog
Data Types
Objective: explains SystemVerilog data types and arrays such as fixed-size array, dynamic array, and associative array.
- Design Elements in SystemVerilog
- Data Types Supported by SystemVerilog
- User-Defined and Enumerated Data Types
- Type Casting
- Strings
- Fixed-Size Arrays
- Dynamic Arrays
- Queues
- Associative Arrays
Tasks and Functions
Objective: explains SystemVerilog tasks and functions (subroutines).
- Introduction to Functions and Tasks
- Tasks
- Functions
- Argument Passing
- Returning from the Subroutine
- Lab 1: Implementing Tasks and Functions – Use a task and function to provide input data for a DUT and perform simulation
SystemVerilog Verification Building Blocks
Objective: explains SystemVerilog verification building blocks such as program, interface, clocking, and packages.
- Interfaces
- Program Block
- Clocking Block
- fork-join
- Packages
- Lab 2: Connecting the Testbench to the DUT – Utilize new SystemVerilog verification building blocks to connect the input data to the DUT
Object-Oriented Modeling
Objective: introduces object-oriented modeling such as encapsulation, inheritance, and polymorphism.
- Introduction to Object-Oriented Programming (OOP)
- Constructor
- Inheritance
- Polymorphism
- Encapsulation and Data Hiding
- Casting
- Using Interfaces in Class
- Lab 3: Object-Oriented Modeling – Use object-oriented programming concepts to create a class for enhancing the verification of the DUT
Randomization
Objective: introduces the following randomization methods: randcase, random sequence, and class-based randomization.
- Introduction to Constrained Randomization
- Randomization Using $urandom and randomize()
- randcase
- Random Sequence
- Class-based Randomization
- Lab 4: Randomization – Create random data as input into the DUT to fully validate the design.
Coverage
Objective: describes functional coverage and usage of covergroup, coverpoint, and bins.
- Coverage Basics
- Covergroups and Coverpoints
- Default and Automatic Bins
- Coverage Options
- Lab 5: Coverage – Create and use a coverage group to validate the code coverage for the DUT. Make adjustments and again validate the coverage
Assertions
Objective: explains the different types of assertions.
- Boolean Expression
- Sequence
- Property
- Assert Statement
- Lab 6: Assertions – Create an assertion to validate all possible conditions are verified for the DUT
DPI: Direct Programming Interface
Objective: introduces the Direct Programming Interface (DPI) to interact with C languages.
- Methods Import and Export
- Data Exchange
- Demo: Direct Programming Interface
Interprocess Communication
Objective: describes the interprocess communication between different processes used to model a complex system.
- Threads
- Mailbox
- Semaphores
