How to Design a High-Speed Memory Interface

Introduces designers to the basic concepts of high-speed memory I/O design,
implementation, and debugging using Xilinx 7 series FPGAs.

TechSource Systems Pte Ltd

Course
Highlights

This two-day course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using Xilinx 7 series FPGAs.

Additionally, students will learn about the tools available for high-speed memory interface design, debug and implementation of high-speed memory interfaces.

The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex®-7 FPGA KC705 board.

TechSource Systems Pte Ltd

Who Should
Attend

FPGA designers and logic designers.

TechSource Systems Pte Ltd

Course
Prerequisites

    • VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
    • Familiarity with logic design: state machines and synchronous design

Helpful/nice to have:

    • Basic knowledge of FPGA architecture and Xilinx implementation tools
    • Familiarity with I/O basics and high-speed I/O standard
    • Familiarity with I/O basics
    • Familiarity with high-speed I/O standards
TechSource Systems Pte Ltd

Course
Benefits

After completing this comprehensive training, you will know how to:

  • Identify the FPGA resources required for memory interfaces
  • Describe different types of memories
  • Utilize the Xilinx tools to generate memory interface designs
  • Simulate memory interfaces with the Xilinx ISim simulator
  • Implement memory interfaces
  • Identify the board design options for the realization of memory interfaces
  • Test and debug your memory interface design
  • Run basic memory interface signal integrity simulations

Partners

TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Course Outline

7 Series FPGAs Family Overview

Objective: describes all of the features in the Xilinx® 7 series FPGAs. It also describes the dedicated IP, subfamilies, and available evaluation kits of the 7 series FPGAs.

  • 7 Series Families
  • Architecture
  • Dedicated IP
  • Family Differentiation
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Memory Devices Overview

Objective: provides an overview of memory devices.

  • Memory Devices Overview
  • Application Examples

7 Series Memory Interface Resources

Objective: explains all the resources required for memory interfaces in Xilinx® 7 series FPGAs.

  • Clocking Resources Overview
  • General Clocking Resources
  • Memory Interface-Specific Clocking Resources
  • I/O Resources Overview
  • SelectIO Interface Resources
  • Other Memory Interface-Specific Resources
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TechSource Systems Pte Ltd

Memory Controller Details and Signals

Objective: explains architectural and functional details of the memory controllers in Xilinx® 7 series FPGAs.

  • Architecture and Functionality
  • Interfaces and Signals

MIG Design Generation

Objective: explains using the Memory Interface Generator (MIG) tool.

  • MIG Tool Usage
  • MIG Tool Results
  • Vivado Design Suite Flow – Core Generation
  • Lab 1: MIG Core Generation – Create a DDR3 memory controller using the Memory Interface Generator (MIG) in the Vivado IP catalog. Customize the soft core memory controller for the board
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

MIG Design Simulation

Objective: explains the simulation options for Memory Interface Generator (MIG) tool designs.

  • MIG Example Design
  • MIG Simulation Options
  • Simulation Parameters
  • Lab 2: MIG Design Simulation – Simulate the memory controller created in Lab 1 using the Vivado simulator or Mentor Graphics QuestaSim simulator.

Memory Design Implementation

Objective: explains the implementation options for Memory Interface Generator (MIG) tool designs.

  • Implementation Guidelines
  • Modifications for Xilinx Evaluation Boards
  • Vivado Design Suite IP Packager
  • Lab 3: MIG Design Implementation – Implement the memory controller created in the previous labs. Modify constraints, synthesize, implement, create the bitstream, program the FPGA, and check the functionality
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Memory Interface Test and Debugging

Objective: discusses test and debugging options for Memory Interface Generator (MIG) tool designs.

  • Debug Tools
  • Simulation Debug
  • Synthesis and Implementation
  • Hardware Debug
  • Lab 4: MIG Design Debugging – Debug the memory interface design utilizing the Vivado logic analyzer

MIG in Embedded Designs

Objective: discusses test the usage of the Memory Interface Generator (MIG) tool in embedded designs.

  • MIG IP in EDK
  • MIG IP in Zynq SoC Devices
  • MIG IP in IP Integrator
  • Lab 5: MIG in IP Integrator – Use the block design editor to include the MIG IP in a given processor design
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Memory Interface Board-Level Design

Objective: explains the board-level design requirements and options for Memory Interface Generator (MIG) tool designs.

  • Design Rules for Memory Interfaces
  • Powering Memories

DDR3 PCB Simulation (optional)

Objective: explains the PCB simulation options for Memory Interface Generator (MIG) tool designs.

  • IBIS Models for Memory SI Analysis
  • SI Tools: Example HyperLynx
  • SI Simulation Topics
  • Lab 6: DDR3 Signal Integrity Analysis – Learn basic signal analysis options to check waveforms and design optimization(optional).
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