FPGA Design Expert

This course offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for beginners to FPGA design.

TechSource Systems Pte Ltd


This three-day provides experience with:

  • Creating a Vivado Design Suite project with source files
  • Simulating a design
  • Performing pin assignments
  • Applying basic timing constraints
  • Synthesizing and implementing
  • Debugging a design
  • Generating and downloading a bitstream onto a demo board

Hands-on Project (1-day) on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor

TechSource Systems Pte Ltd

Who Should

Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the
Vivado Design Suite

TechSource Systems Pte Ltd


  • Basic knowledge of the VHDL or Verilog language
  • Digital design knowledge
TechSource Systems Pte Ltd


After completing this comprehensive training, you will have the necessary skills to:

  • Use the New Project Wizard to create a new Vivado IDE project
  • Describe the supported design flows of the Vivado IDE
  • Generate a DRC report to detect and fix design issues early in the flow
  • Use the Vivado IDE I/O Planning layout to perform pin assignments
  • Synthesize and implement the HDL design
  • Apply clock and I/O timing constraints and perform timing analysis
  • Describe the “baselining” process to gain timing closure on a
  • Use the Schematic and Hierarchy viewers to analyze and
    cross-probe a design
  • Use the Vivado logic analyzer and debug cores to debug a design


TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Course Outline

Introduction to FPGA Architecture, 3D ICs, SoCs, ACAPs

Objective: Overview of FPGA architecture, SSI technology, and SoC device architecture.

  • FPGA architecture
  • major building blocks of FPGAs
  • stacked silicon-based 3D IC devices
  • SoC devices
  • Describe Adaptive Compute Acceleration Platforms (ACAPs)
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

UltraFast Design Methodology: Board and Device Planning

Objective: Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.

  • UltraFastTM Design Methodology checklist to identify common mistakes and decision points throughout the design process
  • which FPGA device resources need particular attention in a design
  • importance of following a proper pin planning methodology
  • what power considerations you need to take into account when planning for the PCB design
  • Fix design issues earlier in the design flow

HDL Coding Techniques

Objective: Covers basic digital coding guidelines used in an FPGA design.

  • use of control signals (sets, resets, and clock enables) can impact your device utilization
  • Describe the benefits of following Xilinx recommendations on resets
  • difference between inference and instantiation
  • design coding to infer the dedicated hardware resources
  • Describe the recommended coding techniques
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Introduction to Vivado Design Flows

Objective: Introduces the Vivado design flows: the project flow and non-project batch flow.

  • various design flows in the Vivado® Design Suite
  • RTL-to-bitstream design flow
  • supported use models in the Vivado Design Suite
  • system-level integration flows

Vivado Design Suite Project-based Flow

Objective: Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design.

  • project mode use model in the Vivado® Design Suite
  • structure and files of a project
  • Vivado Design Suite project in project mode
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Introduction to Vivado Reports

Objective: Generate and use Vivado timing reports to analyze failed timing paths.

  • different reports generated by the Vivado® IDE
  • timing reports and commands used by the Vivado IDE

Behavioral Simulation

Objective: Describes the process of behavioral simulation and the simulation options available in the Vivado® IDE.

  • benefits of behavioral simulation
  • behavioral simulation on a design
  • functionality of a design
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Xilinx Power Estimator Spreadsheet

Objective: Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.

  • estimate power consumption by using the Xilinx Power Estimator (XPE) spreadsheet

Vivado Synthesis and Implementation

Objective: Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.

  • synthesis and implementation options and directives
  • Synthesize and implement an HDL design
  • programs that are available as part of the synthesis and implementation process
TechSource Systems Pte Ltd

Vivado IP Flow

Objective: Customize IP, instantiate IP, and verify the hierarchy of your design IP.

  • managed IP flow in the Vivado® IDE
  • IP catalog from the project to customize and add IP to the design
  • usage of IP output files
  • synthesis options for IP
  • block design container feature in the Vivado IP integrator
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Vivado Design Suite I/O Pin Planning

Objective: Use the I/O Pin Planning layout to perform pin assignments in a design.

  • I/O planning project in the Vivado® IDE
  • Package Pins and I/O Ports windows in the Vivado IDE
  • I/O ports interactivity
  • relationship between I/O banks and the logic in your design

Introduction to Clock Constraints

Objective: Apply clock constraints and perform timing analysis.

  • what is a clock
  • appropriate clock constraints for your design
  • input jitter and clock latency
  • clocks present in the design
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Generated Clocks

Objective: Use the report clock networks report to determine if there are any generated clocks in a design.

  • generated clocks
  • automatically and manually generated clocks
  • relationship between a generated clock and the source clock

I/O Constraints and Virtual Clocks

Objective: Apply I/O constraints and perform timing analysis.

  • appropriate input and output delays for your design
  • virtual clocks for input and output delays in your design
  • timing reports that involve inputs and outputs
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Timing Constraints Wizard

Objective: Use the Timing Constraints Wizard to apply missing timing constraints in a design.

  • Timing Constraints Wizard to create timing constraints
  • completion of timing constraints using the Timing Constraints Wizard

Basics of Clock Gating and Static Timing Analysis

Objective: Describes the basics of clock gating and static timing analysis.

  • basics of clock gating
  • basics of static timing analysis
  • setup and hold slack
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Calculating Setup and Hold Timing

Objective: Reviews setup and hold timing calculations.

  • setup and hold slacks
  • input setup and hold analysis
  • output setup and hold analysis

Introduction to FPGA Configuration

Objective: Describes how FPGAs can be configured.

  • basic FPGA configuration process
  • purpose of each of the FPGA configuration pins
  • FPGA configuration files
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Introduction to the Vivado Logic Analyzer

Objective: Overview of the Vivado logic analyzer for debugging a design.

  • what is Vivado® Logic Analyzer (VLA), as well as the fundamental components that comprise the Vivado debug tool
  • benefits of the Vivado logic analyzer
  • basic probing flows to debug your design

Introduction to Triggering

Objective: Introduces the trigger capabilities of the Vivado logic analyzer.

  • trigger mechanism of the Vivado® logic analyzer
  • using the Run Trigger option
  • captured data using the waveform view
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Debug Cores

Objective: Understand how the debug hub core is used to connect debug cores in a design.

  • ILA core and its properties
  • VIO and IBERT core usage
  • what the debug core hub is and why it is used
  • debug core hub insertion and customization

Introduction to the Tcl Environment

Objective: Introduces Tcl (tool command language).

  • popular uses and benefits of using Tcl commands in an FPGA design development flow
  • how Tcl scripts can be executed from within the interactive environment
  • ways of running the Vivado® IDE with Tcl commands
  • access the help feature
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Tcl Syntax and Structure

Objective: Understand the Tcl syntax and structure.

  • basic syntax and language structure of Tcl
  • Running Tcl commands and scripts interactively and in a shell
  • Tcl command structure
  • substitutions made by the Tcl parser
  • comments and use the puts command
  • strings, brackets, and quoting

Using Tcl Commands in the Vivado Design Suite Project Flow

Objective: Explains what Tcl commands are executed in a Vivado Design Suite project flow.

  • contents of a basic Vivado® IDE script
  • basic Tcl commands in a project-based flow
  • Tcl script
TechSource Systems Pte Ltd

Hands-on Project

FPGA Design Flow Hands-on practices.

TechSource Systems Pte Ltd