TechSource Systems is MathWorks Authorised Reseller and Training Partner
This course offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for beginners to FPGA design.
This three-day provides experience with:
Hands-on Project (1-day) on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor
Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the
Vivado Design Suite
After completing this comprehensive training, you will have the necessary skills to:
Objective: Overview of FPGA architecture, SSI technology, and SoC device architecture.
Objective: Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.
Objective: Covers basic digital coding guidelines used in an FPGA design.
Objective: Introduces the Vivado design flows: the project flow and non-project batch flow.
Objective: Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design.
Objective: Generate and use Vivado timing reports to analyze failed timing paths.
Objective: Describes the process of behavioral simulation and the simulation options available in the Vivado® IDE.
Objective: Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
Objective: Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.
Objective: Customize IP, instantiate IP, and verify the hierarchy of your design IP.
Objective: Use the I/O Pin Planning layout to perform pin assignments in a design.
Objective: Apply clock constraints and perform timing analysis.
Objective: Use the report clock networks report to determine if there are any generated clocks in a design.
Objective: Apply I/O constraints and perform timing analysis.
Objective: Use the Timing Constraints Wizard to apply missing timing constraints in a design.
Objective: Describes the basics of clock gating and static timing analysis.
Objective: Reviews setup and hold timing calculations.
Objective: Describes how FPGAs can be configured.
Objective: Overview of the Vivado logic analyzer for debugging a design.
Objective: Introduces the trigger capabilities of the Vivado logic analyzer.
Objective: Understand how the debug hub core is used to connect debug cores in a design.
Objective: Introduces Tcl (tool command language).
Objective: Understand the Tcl syntax and structure.
Objective: Explains what Tcl commands are executed in a Vivado Design Suite project flow.
FPGA Design Flow Hands-on practices.