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Designing with Versal AI Engine 1 – Architecture and Design Flow
Versal
Designing with Versal AI Engine 1 - Architecture and Design Flow
Learn the Versal® AI Engine architecture & how to program AI Engines
Course
Highlights
This course describes the Versal® AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and AI Engines, and how to analyze the kernel program using various debugger features. The emphasis of this two days course is on:
- Illustrating the AI Engine architecture
- Designing single AI Engine kernels using the Vitis™ unified software platform
- Designing multiple AI kernels using data flow graphs with the Vitis IDE
- Reviewing the data movement between AI Engines, between AI
Engines via memory and DMA, and between AI Engines to programmable logic (PL) - Analyzing and debugging kernel performance
Who Should
Attend
Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using Xilinx devices
Course
Prerequisites
- Comfort with the C/C++ programming language
- Software development flow
- Vitis software for application acceleration development flow
Course
Benefits
After completing this comprehensive training, you will have the
necessary skills to:
- Describe the Versal ACAP architecture at a high level
- Describe the various engines in the Versal ACAP device and the motivation behind the AI Engine
- Describe the architecture of the AI Engine
- Describe the memory access structure for the AI Engine
- Describe the full application acceleration flow with the Vitis tool
- Enumerate the toolchain for Versal AI Engine programming
- Explain what intrinsic functions and AI Engine APIs are
- Program a single AI Engine kernel using the Vitis IDE tool
- Program multiple AI Engine kernels using Adaptive Data Flow (ADF) graphs
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Versal ACAP Architecture
Objective: Provides an overview of the Versal architecture at a high level and describes the various engines in the Versal ACAP, such as the Scalar Engines, Adaptable Engines, and Intelligent Engines. Also describes how the AI Engine in the Versal ACAP meets many dynamic market needs.
- Overview of the Versal ACAP Architecture
Versal AI Engine Architecture
Objective: Introduces the architecture of the AI Engine and describes the AI Engine interfaces that are available, including the memory, lock, core debug, cascaded stream, and AXI-Stream interfaces. Describes the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine arrays.
- Introduction to the Versal AI Engine Architecture
- Versal AI Engine Memory and Data Movement
Vitis Tool Flow
Objective: Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform.
- Versal ACAP Tool Flow
Design Analysis
Objective: Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP.
- Application Partitioning on Versal ACAPs 1
The Programming Model
Objective: Provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions. Describes what intrinsic functions are, the three types of vector management operations using intrinsic functions and AI Engine APIs (load and store, element conversion, and lane insertion/extraction), multiplication functions, and application-specific functions.
- Scalar and Vector Data Types
- AI Engine APIs and Intrinsic Functions
Design Analysis
Objective: Describes the different reports generated by the tool and how to view the reports that help to optimize and debug AI Engine kernels using the Vitis analyzer tool.
- Vitis Analyzer
The Programming Model
Objective: Describes window and streaming APIs and reviews the various window operations for kernels. Also discusses using overlapping data and various data movement use cases. Reviews the AI Engine kernel programming flow for programming and building a single kernel. Also illustrates the steps to create, compile, simulate, and debug a single kernel program using the Vitis IDE tool. Illustrates Versal AI Engine kernel programming in detail, reviewing the scalar kernel code and comparing with vector kernel code that utilizes intrinsic functions and vector data types. Provides the basics of the data flow graph model and graph input specifications for AI Engine programming. Also reviews graph input specifications, such as the number of platforms and ports. Describes the ADF graph in detail and demonstrates the steps to create a graph and set the runtime ratio and graph control APIs from the main application program
- Window and Streaming Data APIs
- The Programming Model: Single Kernel
- The Programming Model: Single Kernel Using Vector Data Types
- The Programming Model: Introduction to the Adaptive Data Flow (ADF) Graph
- The Programming Model: Multiple Kernels Using Graphs