TechSource Systems is MathWorks Authorized Reseller and Training Partner
Introduce the Versal® ACAP network on chip (NoC) to users familiar with Xilinx devices.
This one-day course introduces the Versal® ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.
The emphasis of this course is on:
Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal ACAP devices.
After completing this comprehensive training, you will have the
necessary skills to:
Objective: Introduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices.
Objective: The Versal ACAP has a number of similarities to the Zynq® UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context.
Objective: Review the basic vocabulary and high-level operations of the NoC.
Objective: Provide the first deep dive into the sub-blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic.
Objective: Designers come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox.
Objective: The integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC’s DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use.
Objective: Synthesize everything about the NoC and its DDRMCs,
illustrating how to fine tune the NoC for the best performance.
Objective: Describe how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices.