Designing with the Versal ACAP:
Network on Chip

Introduce the Versal® ACAP network on chip (NoC) to users familiar with Xilinx devices.

TechSource Systems Pte Ltd

Course
Highlights

This one-day course introduces the Versal® ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.

The emphasis of this course is on:

  • Enumerating the major components comprising the NoC
    architecture in the Versal ACAP
  • Implementing a basic design using the NoC
  • Configuring the NoC for efficient data movement
TechSource Systems Pte Ltd

Who Should
Attend

Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal ACAP devices.

TechSource Systems Pte Ltd

Course
Prerequisites

  • Any Xilinx device architecture class
  • Familiarity with the Vivado® Design Suite
TechSource Systems Pte Ltd

Course
Benefits

After completing this comprehensive training, you will have the
necessary skills to:

  • Identify the major network on chip components in the Versal
    ACAP
  • Include the necessary components to access the NoC from the
    PL
  • Configure connection QoS for efficient data movement

Partners

TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorized Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Course Outline

Architecture Overview for Existing Xilinx Users

Objective: Introduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices.

  • Major blocks within the Versal device
  • High-level view of each of the major blocks including its role
  • Connectivity among the major blocks
  • Common use cases
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Versal ACAPs Compared to Zynq UltraScale+ Devices

Objective: The Versal ACAP has a number of similarities to the Zynq® UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context.

  • Primary differences between the Versal® ACAP and Zynq® UltraScale+™ MPSoC/RFSoC architectures
  • New architectural features

NoC Introduction and Concepts

Objective: Review the basic vocabulary and high-level operations of the NoC.

  • NoC architecture in Versal® ACAP devices
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

NoC Architecture

Objective: Provide the first deep dive into the sub-blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic.

  • NoC architecture in Versal® ACAP devices
  • How data enters and exits the NoC structure
  • The components internal to the NoC
  • How users implement the NoC in designs

Design Tool Flow Overview

Objective: Designers come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox.

  • Development platforms for all developers
  • Vitis tool flow for Versal® devices
  • Full application acceleration flow for the Vitis platform
  • Toolchain for Versal AI Engine programming
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

NoC DDR Memory Controller

Objective: The integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC’s DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use.

  • DDR memory controllers connected to the NoC
  • Relationship between the NoC and DDRMC
  • Scope and capability of the DDR memory controller
  • Vivado® IP integrator to set up the DDR memory controller
  • Multiple DDRMCs to interleave memory
  • Address mapping

NoC Performance Tuning

Objective: Synthesize everything about the NoC and its DDRMCs,
illustrating how to fine tune the NoC for the best performance.

  • Analyze and configure NoC architecture in Versal® ACAP devices
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

System Design Migration

Objective: Describe how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices.

  • Several approaches to migrating existing designs to the Versal® ACAP
  • Maps tools to design types
  • How “ground-up” designs can be approached
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