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Become acquainted with the various solutions that Xilinx offers for
This two-day course help engineers to become acquainted with the various solutions that Xilinx offers for Ethernet connectivity.
The course covers:
Engineers who would like to come up to speed on utilizing Xilinx Ethernet connectivity solutions.
After completing this comprehensive training, you will have the necessary skills to:
Objective: reviews the history of the Ethernet standard and the OSI protocol layers.
Objective: Enter MATLAB commands, with an emphasis on creating variables, accessing and manipulating data in variables, and creating basic visualizations. Collect MATLAB commands into scripts for ease of reproduction and experimentation.
Objective: focus on the establishment of a link with auto-negotiation and on the recovery of a clock from a serial data stream.
Objective: covers not just the transmitter and receiver interfaces, but also the associated control frames.
Objective: illustrates the Ethernet solutions available from Xilinx and how you can access these solutions through the Vivado® IP catalog.
Objective: explores Xilinx Ethernet solutions at the 10, 100, and 1000 Mbps rates, focusing on the applications that use these most popular Ethernet data rates.
Objective: explores the use of an embedded processor in an Ethernet-based design. Included will be a simple design with the Ethernet data flow through the processor, an example using DMA, and an example showing how the Zynq® AP SoC provides ready solutions.
Objective: introduces the Xilinx standalone MAC core IP solutions for 10G speeds and above. The presentation is divided into two sections, 10G/25G MAC and 40G/100G offerings.
Objective: finishes the class with a few miscellaneous items, an introduction to the various Ethernet MACless cores in the Vivado® IP catalog, and a summary of the AVB protocol.