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TechSource Systems is MathWorks Authorised Reseller and Training Partner
Advanced VHDL
Increase VHDL proficiency by learning advanced techniques for writing
more robust and reusable code.
Course
Highlights
This comprehensive two days course is targeted toward designers who already have some experience with VHDL.
Who Should
Attend
VHDL users with intermediate knowledge of VHDL.
Course
Prerequisites
- Designing with VHDL course or equivalent knowledge of modeling, simulation, and RTL coding
- At least six months of coding experience beyond an introductory course
Course
Benefits
After completing this comprehensive training, you will have the necessary skills to:
- Write efficient and reusable RTL, testbenches, and packages
- Create self-testing testbenches
- Create realistic models
- Use the text I/O capabilities of the VHDL language
- Store simulation data dynamically
- Create parameterized code for design reuse
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
VHDL Overview
- efficient and reusable RTL, testbenches, and packages
- self-testing testbenches
- realistic models
- text I/O capabilities of the VHDL language
- Storing simulation data dynamically
- parameterized code for design reuse
Simulation Concepts
- differences between analysis, elaboration, and execution
- appropriate time to use transport and inertial delay
- how concurrency is modeled
- Vivado® simulator for the various simulation points
Advanced Data Types
- Natural
- Unconstrained
- Aliases
- Shared variables
- Protected types
- User-defined types: records, arrays, types, subtypes
- Physical types
- Access
- File
Subprograms and Design Attributes
- impure functions
- how to use procedure-class parameters
- design attributes
- advantages of using subprograms
Access Type Techniques and Blocks
- commonly used techniques using access types
- how blocks can be used to associate logic
File I/O
- VHDL Text IO package for reading and writing to text files
Advanced Techniques in VHDL
- existing IEEE packages and third-party packages
- Implement controlled jitter and spectrum spreading
- real-world timing problems, including Trace-length mismatches and Asynchronous stimulus
Supporting Multiple Platforms
- mechanisms for supporting alternate architectures
- proper syntax of conditional generate and configuration statements and their proper use
- alternate methods for supporting multiple platforms (directory structures and scripts
- set up a multiple-architecture design in the Vivado® Design Suite
Non-Integer Numbers
- contents and relevance of the IEEE-proposed standard for synthesis of floating point numbers
- alternatives to floating point numbers
- theory behind floating point representation
