Customise Your Training
TechSource Systems is MathWorks Sole and Authorised Distributor and Training Partner
Designing with Ethernet MAC Controllers
Become acquainted with the various solutions that Xilinx offers for
Ethernet connectivity
Course
Highlights
This two-day course help engineers to become acquainted with the various solutions that Xilinx offers for Ethernet connectivity.
The course covers:
- Learning the basics of the Ethernet standard, protocol, and OSI
model - Performing simulation to understand fundamental principles
- Assessing hardware design considerations and software development requirements
- Becoming familiar with Ethernet IP core design architectures, core IP port naming conventions, and signal waveforms
Who Should
Attend
Engineers who would like to come up to speed on utilizing Xilinx Ethernet connectivity solutions.
Course
Prerequisites
- FPGA design experience
- Completion of the Designing FPGAs Using the Vivado Design Suite 1 course or equivalent knowledge of Xilinx Vivado® software implementation tools
- Basic understanding of microprocessors
- Some HDL modeling experience
Course
Benefits
After completing this comprehensive training, you will have the necessary skills to:
- Describe the basics of the Ethernet standard, protocol, and OSI model
- Identify the various solutions that Xilinx offers for Ethernet connectivity
- Utilize various Ethernet cores either in a standalone mode or as a peripheral in a processor-based design
- Use simulation to become familiar with IP core port names and operations
- Explore the Xilinx-provided example software application using the lwIP stack
- Integrate Ethernet IP into your design using the Vivado Design Suite
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Ethernet Basics
Objective: reviews the history of the Ethernet standard and the OSI protocol layers.
- Networking Standards
- OSI Model
- Ethernet Frames
- Media Access Control
Network Protocols, Ethernet Interfaces, and Hardware
Objective: Enter MATLAB commands, with an emphasis on creating variables, accessing and manipulating data in variables, and creating basic visualizations. Collect MATLAB commands into scripts for ease of reproduction and experimentation.
- Network Protocols
- Ethernet Interfaces
- Ethernet Hardware
- Lab 1: Exploring Ethernet Frames – Perform a functional simulation of the Tri-Mode Ethernet MAC LogiCORE™ IP
Physical Layer
Objective: focus on the establishment of a link with auto-negotiation and on the recovery of a clock from a serial data stream.
- Auto-Negotiation
- 8B/10B Encoding/Decoding
- MII, GMII, RGMII Interface
- MDIO, TBI, SGMII, XGMII, XGXS, XAUI Interface
- Signaling
AXI Interface
Objective: covers not just the transmitter and receiver interfaces, but also the associated control frames.
- Ethernet PCS/PMA
- MAC Transmitter Interface
- MAC Receiver Interface
- Flow Control
- Management Interface
- Lab 2: Advanced Ethernet Frames – Perform a functional simulation of a Vivado Design Suite project, based on the TriMode Ethernet MAC example design, that is provided with several simulation testbenches
Xilinx EMAC Offerings
Objective: illustrates the Ethernet solutions available from Xilinx and how you can access these solutions through the Vivado® IP catalog.
- Xilinx EMAC Solutions
- Vivado IP Catalog Delivery
- Management Interface
- Lab 3: AXI Ethernet Example Design – Create a new Vivado Design Suite project, use the IP catalog tool to generate an AXI Ethernet Subsystem core, and open the Xilinx-provided example design
10/100/1000 EMAC Solutions
Objective: explores Xilinx Ethernet solutions at the 10, 100, and 1000 Mbps rates, focusing on the applications that use these most popular Ethernet data rates.
- AXI Ethernet Lite MAC (10/100) IP
- Tri Mode Ethernet MAC (10/100/1000) IP
- AXI Ethernet MAC (10/100/100) IP
Processor-Based Ethernet
Objective: explores the use of an embedded processor in an Ethernet-based design. Included will be a simple design with the Ethernet data flow through the processor, an example using DMA, and an example showing how the Zynq® AP SoC provides ready solutions.
- Introduction to Processor Based Ethernet Designs
- Basic MicroBlaze Processor Design
- DMA
- Ethernet for the Zynq AP SoC
- Lab 4: Processor-Based Ethernet Design – Use the Vivado IP integrator tool to create an Ethernet-based embedded system
10/25/40/100GE Solutions
Objective: introduces the Xilinx standalone MAC core IP solutions for 10G speeds and above. The presentation is divided into two sections, 10G/25G MAC and 40G/100G offerings.
- 10G/25G Solutions
- 40G and 100G Solutions
Ethernet Odds and Ends
Objective: finishes the class with a few miscellaneous items, an introduction to the various Ethernet MACless cores in the Vivado® IP catalog, and a summary of the AVB protocol.
- Ethernet Misc
- Misc Ethernet IP Cores
- Ethernet Audio Video Bridging (AVB)
- Lab 5: Analyzing 10GE MAC Frames – Investigate the PHY and client interfaces of the 10-Gigabit Ethernet MAC LogiCORE IP, available in the Vivado IP catalog, by performing a functional simulation.