Xilinx

SOC and MPSOC

Zynq UltraScale+ MPSoC for the Hardware Designer

Course Description

This course provides hardware designers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.

The emphasis is on:

▪ Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)

▪ Reviewing the various power domains and their control structure

▪ Illustrating the processing system (PS) and programmable logic (PL) connectivity ▪

Utilizing QEMU to emulate hardware behavior 

Duration

2 days

Level

Embedded Hardware 3

Who Should Attend

Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device. 

Course Prerequisites

​▪ Suggested: Understanding of the Zynq-7000 architecture

▪ Basic familiarity with embedded software development using C (to support testing of specific architectural elements) 

Software Tools

▪ Vivado Design Suite 2020.1

▪ Vitis unified software platform 2020.1

▪ Hardware emulation environment:

○ VirtualBox

○ QEMU

○ Ubuntu desktop

○ PetaLinux 

Hardware

​Zynq UltraScale+ MPSoC ZCU104 board*

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

▪ Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)

▪ List the various power domains and how they are controlled

▪ Describe the connectivity between the processing system (PS) and programmable logic (PL)

▪ Utilize QEMU to emulate hardware behavior 

Course Outline

Day 1

Application Processing Unit

Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster is configured and managed. 
▪ HW-SW Virtualization

Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.

Real-Time Processing Unit

Focuses on the real-time processing module (RPU) in the PS, which is comprised of a pair of Cortex processors and supporting elements. 

▪ QEMU

Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available. 

▪ Booting

How to implement the embedded system, including the boot process and boot image creation. 

First Stage Boot Loader

Demonstrates the process of developing, customizing, and debugging this mandatory piece of code. 

Day 2

Video

Introduction to video, video codecs, and the Video Codec Unit available in the Zynq UltraScale MPSoC.

System Protection

Covers all the hardware elements that support the separation of software domains.

Clocks and Resets

Overview of clocking and reset, focusing more on capabilities than specific implementations. 

AXI

Understanding how the PS and PL connect enables designers to create more efficient systems. 

Power Management

Overview of the PMU and the power-saving features of the device.

Partners 

Upcoming Program

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products