SOC and MPSOC
Zynq UltraScale+ MPSoC for the System Architect
This two-day course is structured to provide system architects with an overview of the capabilities and support for the Zynq UltraScale+ MPSoC family.
Who Should Attend
System architects interested in understanding the capabilities and ecosystem of the Zynq® UltraScale+™ MPSoC device.
Suggested: Understanding of the Zynq-7000 architecture
Familiarity with embedded operating systems
Vivado® Design Suite 2016.3
May require special Zynq UltraScale+ MPSoC family license
Hardware emulation environment:
Host computer for running the above software*
After completing this training, you will know how to:
Effectively use power management strategies and leverage the capabilities of the platform management unit (PMU)
Identify mechanisms to secure and safely run the system
Outline the high-level architecture of the devices
Define the boot sequences appropriate to the needs of the system
1.1 Zynq UltraScale+ MPSoC Overview
Overview of the Zynq UltraScale+ MPSoC device.
1.2 Zynq UltraScale+ MPSoC HW-SW Virtualization
Covers the hardware and software elements of virtualization. The lab demonstrate how hypervisors can be used.
Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available.
1.4 Zynq UltraScale+ MPSoC Security and Software
Introduction to the purpose and API of the Software Test Library.
2.1 Zynq UltraScale+ MPSoC Power Management
Overview of the PMU and the power-saving features of the device.
2.2 Zynq UltraScale+ MPSoC System Coherency
Learn how information is synchronized within the API and through the ACE/AXI ports.
2.3 Zynq UltraScale+ MPSoC DDR and QoS
Understand how DDR can be configured to provide the best performance for your system.
2.4 Zynq UltraScale+ MPSoC Booting
How to implement the embedded system, including the boot process and boot image creation.
2.5 Zynq UltraScale+ MPSoC Ecosystem Support
Overview of supported operating systems, software stacks, hypervisors, etc.