FPGA Design

VHDL & FPGA Design Expert

Course Description

‘VHDL & FPGA Design’ is a comprehensive training package that comprises of 2 course modules: Designing with VHDL and Designing FPGAs Using the Vivado Design Suite 1.Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness. 

Designing with VHDL (3-day) provides a thorough introduction to the VHDL language. The emphasis is on writing efficient hardware designs, performing high-level HDL simulations,employing structural, register transfer level (RTL), and behavioral coding styles, targeting Xilinx devices specifically and FPGA devices in general, utilizing best coding practices.

Designing FPGAs Using the Vivado Design Suite 1 (2-day) offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.

The course provides experience with creating a Vivado Design Suite project with source files, simulating a design, performing pin assignments, applying basic timing constraints, synthesizing and implementing, debugging a design, generating and downloading a bitstream onto a demo board.

Hands-on Project (1-day) on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor.


Upcoming Program

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products

Who Should Attend

Digital designers who are interested in FPGA design training and want to use VHDL effectively for modeling, design, and synthesis of digital designs and learn to use Xilinx FPGAs.


6 days 

Course Prerequisites

  • Basic digital design knowledge

Skills Gained

After completing this training, you will have the necessary skills to:

Design with VHDL

  • Implement the VHDL portion of coding for synthesis

  • Identify the differences between behavioral and structural coding styles

  • Distinguish coding for synthesis versus coding for simulation

  • Use scalar and composite data types to represent information

  • Use concurrent and sequential control structure to regulate information flow

  • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)

  • Simulate a basic VHDL design

  • Write a VHDL testbench and identify simulation-only constructs

  • Identify and implement coding best practices

  • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA

  • Create and manage designs within the Vivado Design Suite environment 

Designing FPGAs Using the Vivado Design Suite 1

  • Take advantage of the primary 7 series FPGA architecture resources

  • Use the Project Manager to start a new project

  • Identify the available Vivado IDE design flows (project based and non-project batch)

  • Identify file sets (HDL, XDC, simulation)

  • Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer

  • Synthesize and implement an HDL design

  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)

  • Build custom IP with the IP Library utility

  • Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)

  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

  • Describe and analyze common STA reports

  • Identify synchronous design techniques

  • Describe how an FPGA is configured

Course Outline

Day 1

Introduction to VHDL

Discusses the history of the VHDL language and provides an overview of the different features of VHDL. {Lecture}

VHDL Design Units

Provides an overview of typical VHDL code, covering design units such as libraries, packages, entities, architectures, and configuration. {Lecture, Lab}

VHDL Objects, Keywords, Identifiers

Discusses the data objects that are available in the VHDL language as well as keywords and identifiers. {Lecture}

Scalar Data Types

Covers both intrinsic and commonly used data types. {Lecture}

Composite Data Types

Covers composite data types (arrays and records). {Lecture}

VHDL Operators

Reviews all VHDL operator types. {Lecture}

Concurrency in VHDL

Describes concurrent statements and how signals help in achieving concurrency. {Lecture}

Concurrent Assignments

Covers both conditional and unconditional assignments. {Lecture, Lab}

Processes and Variables

Introduces sequential programming techniques for a concurrent language. Variables are also discussed. {Lecture, Demo, Lab}

Day 2

Conditional Statements in VHDL: if/else, case

Describes conditional statements such as if/else and case statements. {Lecture, Lab}

Sequential Looping Statements

Introduces the concept of looping in both the simulation and synthesis environments. {Lecture, Lab}

Delays in VHDL: Wait Statements

Covers the wait statement and how it controls the execution of the process statement. {Lecture}

Introduction to the VHDL Testbench

Introduces the concept of the VHDL testbench to verify the functionality of a design. {Lecture, Lab}

VHDL Assert Statements

Describes the concept of VHDL assertions. {Lecture}

VHDL Attributes

Describes attributes, both predefined and user defined. {Lecture}

VHDL Subprograms

Covers the use of subprograms in verification and RTL code to model functional blocks. {Lecture}

VHDL Functions

Describes functions, which are integral to reusable and maintainable code. {Lecture, Lab}

VHDL Procedures

Describes procedures, common constructs that are also important for reusing and maintaining code. {Lecture}

Day 3

VHDL Libraries and Packages

Demonstrates how libraries and packages are declared and used. {Lecture, Lab}

Interacting with the Simulation

Describes how to interact with a simulation via text I/O. {Lecture}

Finite State Machine Overview

Provides an overview of finite state machines, one of the more commonly used circuits. {Lecture}

Day 4

Introduction to FPGA Architecture, 3D ICs, SoCs

Overview of FPGA architecture, SSI technology, and SoC device architecture. {Lecture}

UltraFast Design Methodology: Board and Device Planning

Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist. {Lecture, Demo}

HDL Coding Techniques

Covers basic digital coding guidelines used in an FPGA design. {Lecture}

Introduction to Vivado Design Flows

Introduces the Vivado design flows: the project flow and non-project batch flow. {Lecture}

Vivado Design Suite Project-based Flow

Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design. {Lecture, Lab}

Behavioral Simulation

Describes the process of behavioral simulation and the simulation options available in the Vivado® IDE. {Lecture}

Vivado Synthesis and Implementation

Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board. {Lecture, Lab}

Basic Design Analysis in the Vivado IDE

Use the various design analysis features in the Vivado Design Suite. {Lab, Demo}

Vivado Design Rule Checks

Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations. {Lab}

Vivado Design Suite I/O Pin Planning

Use the I/O Pin Planning layout to perform pin assignments in a design. {Lecture, Lab}

Vivado IP Flow

Customize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Demo, Lab}

Day 5

Introduction to Clock Constraints

Apply clock constraints and perform timing analysis. {Lecture, Demo, Lab}

Generated Clocks

Use the report clock networks report to determine if there are any generated clocks in a design. {Lecture, Demo} I/O I/O Constraints and Virtual Clocks

Apply I/O constraints and perform timing analysis. {Lecture, Lab}

Timing Constraints Wizard

Use the Timing Constraints Wizard to apply missing timing constraints in a design. {Lecture, Lab}

Introduction to Vivado Reports

Generate and use Vivado timing reports to analyze failed timing paths. {Lecture, Demo}

Basics of Static Timing Analysis

Describes the basics of static timing analysis. {Lecture}

Calculating Setup and Hold Timing

Reviews setup and hold timing calculations. {Lecture}

Xilinx Power Estimator Spreadsheet

Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}

Introduction to FPGA Configuration

Describes how FPGAs can be configured. {Lecture}

Introduction to the Vivado Logic Analyzer

Overview of the Vivado logic analyzer for debugging a design. {Lecture, Demo}

Introduction to Triggering

Introduces the trigger capabilities of the Vivado logic analyzer. {Lecture}

Debug Cores

Understand how the debug hub core is used to connect debug cores in a design. {Lecture}

Introduction to the Tcl Environment

Introduces Tcl (tool command language). {Lecture, Lab}

Using Tcl Commands in the Vivado Design Suite Project Flow

Explains what Tcl commands are executed in a Vivado Design Suite project flow. {Lecture, Demo}

Tcl Syntax and Structure

Understand the Tcl syntax and structure. {Lecture}

Day 6

  • Full FPGA Design Flow Hands-on Project