Xilinx

FPGA Design

VHDL & FPGA Design Expert

Course Description

‘VHDL & FPGA Design’ is a comprehensive training package that comprises of 2 course modules: Designing with VHDL and Essentials of FPGA. Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.

Designing with VHDL (3-day) provides a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, Register Transfer Level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.

Essentials of FPGA Design (2-day) is specially designed for designers new to FPGAs design or programmable logic. Build an effective FPGA design using synchronous design techniques, instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing constraints, and use the Vivado® Design Suite to build, synthesize, implement, and download a design.

Hands-on Project (1-day) on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor.

Partners 

Upcoming Program

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products

Who Should Attend

Digital designers who are interested in FPGA design training and want to use VHDL effectively for modeling, design, and synthesis of digital designs and learn to use Xilinx FPGAs.

Duration

6 days 

Course Prerequisites

  • Basic digital design knowledge

Skills Gained

After completing this training, you will know how to:

Design with VHDL

  • Implement the VHDL portion of coding for synthesis

    • Identify the differences between behavioral and structural coding styles

    • Distinguish coding for synthesis versus coding for simulation

    • Use scalar and composite data types to represent information

    • Use concurrent and sequential control structure to regulate information flow

    • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)

  • Simulate a basic VHDL design

    • Write a VHDL testbench and identify simulation-only constructs

  • Identify and implement coding best practices

    • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA

    • Create and manage designs within the Vivado Design Suite environment

Essentials of FPGA

  • Take advantage of the primary 7 series FPGA architecture resources

  • Use the Project Manager to start a new project

  • Identify the available Vivado IDE design flows (project based and non-project batch)

  • Identify file sets (HDL, XDC, simulation)

  • Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer

  • Synthesize and implement an HDL design

  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)

  • Build custom IP with the IP Library utility

  • Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)

  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

  • Describe and analyze common STA reports

  • Identify synchronous design techniques

  • Describe how an FPGA is configured

Course Outline

Day 1

1.1 The "Shape" of VHDL 
1.2 Demo: Multiplexer
1.3 Lab 1: Using the Tools 
1.4 Data Types
1.5 Concurrent Operations 
1.6 Lab 2: Using Concurrent Statements 
1.7 Processes and Variables 
1.8 Lab 3: Designing a Simple Process

Day 2

2.1 Introduction to Testbenches
2.2 Vivado Simulator Basics 
2.3 Lab 4: Simulating a Simple Design 
2.4 Creating Memory
2.5 Lab 5: Building a Dual-Port Memory 
2.6 Finite State Machines 
2.7 Lab 6: Building a Moore Finite State Machine 
2.8 Targeting Xilinx FPGAs 
2.9 Lab 7: Xilinx Tool Flow

Day 3

3.1 Loops and Conditional Elaboration 
3.2 Lab 8: Using Loops 
3.3 Attributes
3.4 Functions and Procedures
3.5 Packages and Libraries 
3.6 Lab 9: Building Your Own Package
3.7 Interacting with the Simulation
3.8 Writing a Good Testbench
3.9 Lab 10: Building a Meaningful Testbench

Module 2: FPGA Design Expert

Day 4

  • Design Methodology Summary

  • Basic FPGA Architecture

  • Vivado IDE Features and Benefits

  • Introduction to the Vivado Design Suite

  • Vivado IDE Project Manager and IP Library

  • Vivado IDE Tool Overview

  • Lab 1: Vivado Tool Overview

  • Vivado IDE Synthesis and Reports

  • Vivado IDE Implementation and Static Timing Analysis

  • Lab 2: Vivado Synthesis and Implementation

Day 5

  • Designing with FPGA Resources

  • Clocking Resources

  • Lab 3a: Designing with FPGA Resources

  • Lab 3b: Creating an IP Integrator Subsystem Design

  • Basic Timing Constraints (XDC)

  • Timing Reports

  • Lab 4: Basic XDC and Timing Reports

  • Synchronous Design Techniques

  • FPGA Configuration

  • Appendix: SystemVerilog

  • Appendix: Design Methodology

  • Appendix: HDL Coding Techniques

Day 6

  • Full FPGA Design Flow Hands-on Project

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