VHDL Complete



Upcoming Program

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TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products

Course Description

This is a comprehensive course that covers the application of VHDL for programmable logic and ASIC design. Based on Xilinx industry standard, this total training package can be considered as the minimum training requirement for project readiness.

The course is based on a 5-day agenda. Comprising 2 modules, it can be taken in two stages by attending the individual modules or the full 5-day training package with an interval of at least 2 months.


  • Designing with VHDL (3-day) is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, Register Transfer Level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.


  • Advanced VHDL (2-day) is specially designed to increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This is targeted toward designers who already have some experience with VHDL. The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating

parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.


5 days (10:00am - 5:30pm)

Course Prerequisites

  • Basic digital design knowledge

Skills Gained

Designing with VHDL

  • Implement the VHDL portion of coding for synthesis

          o Identify the differences between behavioral and structural coding styles ​

          o Distinguish coding for synthesis versus coding for simulation 

          o Use scalar and composite data types to represent information 

          o Use concurrent and sequential control structure to regulate information flow 

          o Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures) 

  • Simulate a basic VHDL design

          o Write a VHDL testbench and identify simulation-only constructs 

  • Identify and implement coding best practices

          o Optimize VHDL code to target specific silicon resources within the Xilinx FPGA 

  • Create and manage designs within the ISE software environment  

Advanced DHL

  • Write efficient and reusable RTL, testbenches, and packages

  • Create self-testing testbenches

  • Create realistic models

  • Use the text IO capabilities of the VHDL language

  • Store simulation data dynamically

  • Create parameterized designs

  • Create parameterized code for design reuse


Course Outline

Module 1: Designing with VHDL

Day 1​

1.1 The "Shape" of VHDL 
1.2 Demo: Multiplexer
1.3 Lab 1: Using the Tools 
1.4 Data Types
1.5 Concurrent Operations 
1.6 Lab 2: Using Concurrent Statements 
1.7 Processes and Variables 
1.8 Lab 3: Designing a Simple Process

Day 2

2.1 Introduction to Testbenches
2.2 Vivado Simulator Basics 
2.3 Lab 4: Simulating a Simple Design 
2.4 Creating Memory
2.5 Lab 5: Building a Dual-Port Memory 
2.6 Finite State Machines 
2.7 Lab 6: Building a Moore Finite State Machine 
2.8 Targeting Xilinx FPGAs 
2.9 Lab 7: Xilinx Tool Flow

Day 3

3.1 Loops and Conditional Elaboration 
3.2 Lab 8: Using Loops 
3.3 Attributes
3.4 Functions and Procedures
3.5 Packages and Libraries 
3.6 Lab 9: Building Your Own Package
3.7 Interacting with the Simulation
3.8 Writing a Good Testbench
3.9 Lab 10: Building a Meaningful Testbench

Module 2: FPGA Design Expert 

Day 4

4.1 Review of Current Knowledge 

4.2 Simulation Concepts 

4.3 Advanced Data Types

4.4 Subprogrames and Design Attributes

4.5 Lab 1: Flexible Functions

4.6 Access Type Techniques and Blocks 

4.7 Lab 2: Linked Lists with Access Types

4.8 Utilizing File IO

4.9 Lab 3: TextIO Techniques 


Day 5

5.1 Cool Stuff with VHDL
5.2 Lab 4: Creating Real-World Simulations Supporting Multiple Platforms
5.3 Lab 5: Supporting Multiple Platforms Non-Integer Numbers
5.4 Lab 6: Implementing Fixed and Floating Point Numbers
5.5 Course Summary