Xilinx

FPGA Design

Design with the UltraScale and UltraScale+ Architectures

Course Description

This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers. The emphasis is on:

  • Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources

  • Describingimprovements to the dedicated transceivers and Transceiver Wizard

  • Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities

  • Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado® DesignSuite

Partners 

Upcoming Program

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products

Level

FPGA3

Duration

2 Days

Who Should Attend

Anyone who would like to build a design for the UltraScale™ or UltraScale+™ device family

Course Prerequisites

Software Tools

Vivado HL Design or System Edition 2020.1

Hardware

  • Architecture:UltraScale+ UltraScale FPGAs*

  • Demo board: None*

* This course focuses on the UltraScale architecture. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Take advantage of the primary UltraScale architecture resources

  • Describe the new CLB capabilities and the impact that they make on your HDL coding style

  • Define the block RAM, FIFO, and DSP resources available

  • Describe the UltraRAM features

  • Properly design for the I/O and SERDES resources

  • Identify the MMCM, PLL, and clock routing resources included

  • Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces

  • Describe the additional features of the dedicated transceivers

  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

Day 1

  • Introduction to the UltraScale Architecture - Review the UltraScalearchitecture, which includes enhanced CLB resources, DSP resources, etc.

  • UltraScale Architecture CLB Resources - Examine the CLB resources, such as the LUT and the dedicated carry chain, in the UltraScale architecture.

  • HDL Coding Techniques - Covers basic digital coding guidelines used in an FPGA design.

  • UltraScale Architecture Clocking Resources-Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks.

  • FPGA Design Migration - Migrate an existing 7 series design to the UltraScale architecture.

  • Clocking Migration - Migrate a 7 series design to the UltraScale architecture with a focus on clocking resources. UltraScale Architecture Block RAM Memory Resources -Review the block RAM resources in the UltraScale architecture.

  • UltraScale Architecture FIFO Memory Resources-Review the FIFO resources in the UltraScale architecture.

  • UltraRAM Memory - Use UltraRAM for a design requiring a larger memory size than block RAM.

  • High Bandwidth Memory - Use high bandwidth memory (HBM) for applications requiring high bandwidth.

Day 2

  • Pipeline for Performance: DATAFLOW Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible.

  • Optimizing Structures for Performance Learn the performance limitations caused by arrays in your design. You will also learn some optimization techniques to handle arrays for improving performance.

  • Data Pack and Data Dependencies Learn how to use DATA_PACK and DEPENDENCE directives to overcome the limitations caused by structures and loops in the design.

  • Vivado HLS Tool Default Behavior: Latency Describes the default behavior of the Vivado HLS tool on latency and throughput.

  • Reducing Latency Describes how to optimize the C design to improve latency.

  • Improving Area and Resource Utilization Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization.

  • HLx Design Flow –System Integration Describes the traditional RTL flow versus the Vivado HLx design flow.

  • Vivado HLS Tool C Libraries: Arbitrary Precision Describes the Vivado HLS tool support for the C/C++ languages, as wellas arbitrary precision data types.

  • Hardware Modeling Explains hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class.

  • Using Pointers in the Vivado HLS Tool Explains the use of pointers in the design and workarounds for some of the limitations.