UltraFast Design Methodology
This course describes the FPGA design best practices and skills to be successful using the Vivado® Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.
TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products
Who Should Attend
Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.
Some knowledge of FPGA design techniques is helpful
Experience with the Vivado Design Suite or attendance of one of our existing Vivado Design Suite training courses is required
Intermediate knowledge of Verilog or VHDL
Vivado Design or System Edition 2016.1
Architecture: UltraScale™ and 7 series FPGAs**
Demo board: None*
After completing this comprehensive training, you will have the necessary skills to:
Describe the UltraFast Design Methodology Checklist
Identify key areas to optimize your design to meet your design goals and performance objectives
Define a properly constrained design
Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
Build resets into your system for optimum reliability and design speed
Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
Identify timing closure techniques using the Vivado Design Suite
Describe how the UltraFast design methodology techniques work effectively through case studies and lab experience.
1.1 UltraFast Design Methodology Case Study
1.2 Demo 1: UltraFast Design Methodology Checklist
1.3 UltraFast Design Methodology
1.4 HDL Coding Techniques
1.6 Lab 1: Resets
Investigate the proper design and use of resets. Examine the impact of seeing a design built originally with asynchronous resets, having resets removed, and finally with synchronous resets only used where necessary.
1.8 Lab 2: Inference
Evaluate the implementation results of a design that uses asynchronous resets and infers more dedicated hardware resources when resets are selectively removed from the design. You will also learn how to infer the DSP hardware resources for other common functions required by most FPGA designs.
1.9 Synchronization Circuits
2.0 Demo 2: Synchronization Circuits
2.2 Demo 3: Baselining
2.3 Timing Closure and Design Conversion Lab Introduction
2.4 Lab 3: Timing Closure and Design Conversion
Learn how a generic processor design was optimized for the 7 series device architecture with basic design changes that impacted the dedicated hardware usage, design speed, and the device utilization.
2.6 Lab 4: Pipelining
Explore how pipelining can improve performance (increased clock rate and throughput) and facilitate timing closure.
2.7 Register Duplication
2.8 Physical Optimization
2.9 I/O Flip-Flops