SystemVerilog for Design and Verification

Course Description

This course presents SystemVerilog for design and verification. SystemVerilog is an extension of
Verilog that combines both hardware description and verification into one language.


The emphasis is on:

  • SystemVerilog introduces some new constructs that allow more robust RTL coding and better
    compile-time checks compared to Verilog.

  • SystemVerilog provides a number of new features, such as object-oriented modeling, constrained
    randomization, functional coverage, assertions and others that enable powerful verification methods for increasingly complex chips.

  • SystemVerilog is also used to develop UVM to provide standard verification methodology. Verification can be performed with SystemVerilog alone, or in combination with UVM. 



TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products

Upcoming Program

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3 Days

Who To Attend

This course is intended for those who are involved in digital design and verification. They include chip design engineers, verification engineers and technical managers.


  • Experienced Verilog user or completion of the Designing with Verilog course.

  • Verilog design experience or completion of Designing with Verilog.

Software Tools

Simulator, e.g. from Cadence, Mentor or Synopsys


  • Architecture: N/A*

  • NA

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the features and benefits of using SystemVerilog for RTL design

  • Identify the new data types supported in SystemVerilog

  • Explain how to use structures and arrays

  • Describe the new procedural blocks and analyze the affected synthesis results

  • Define the enhancements and ability to reuse tasks, functions, and packages

  • Identify how to simplify module definitions and instantiations using interfaces

  • Describe the advantages and enhancements to SystemVerilog to support verification

  • Define the new data types available in SystemVerilog

  • Analyze and use the improvements to tasks and function

  • Discuss and use the various new verification building blocks available in SystemVerilog

  • Describe object-oriented programming and create a class-based verification environment

  • Explain the various methods for creating random data

  • Create and utilize random data for generating stimulus to a DUT

  • Identify how SystemVerilog enhances functional coverage for simulation verification

  • Utilize assertions to quickly identify correct behavior in simulation

  • Identify how the direct programming interface can be used with C/C++ in a verification environment.

Course Outline

Day 1

       SV Basic Types

  • Literals, Variables and Constants

  • 2-State and 4-State Types

  • Parameter, Localparam, Const

  • Simulation Time and Format

  • String Operators and Methods

  • Enumeration Data Types and Methods


  • Operator Classifications

  • Arithmetic, Bitwise, Reduction

  • Shift, Logical, Relational, Equality

  • Implicit, Static and Dynamic Casting
    Assignments and Statements

  • Procedural and Continuous Assignments

  • unique-if, unique0-if, priority-if

  • case, casex, casez

  • unique-case, unique0-case, priority-case

  • Set Membership Case

  • Loop Statements

    Tasks and Functions

  • Task Declarations and Arguments

  • Static and Automatic Tasks Static and Automatic Variables

  • Pass by Value and Reference

  • Automatic and Constant Functions

  • always_comb and always @*

  • always_ff and always_latch

  • fork-join, join_any, join_none

  • Level-sensitive and Edge Control

  • Process Control and Event Synchronization

Day 2

       Arrays and Structures

  • Packed and Unpacked Arrays

  • Dynamic and Associative Arrays

  • Queue and Queue Methods

  • Packed and Unpacked Structures
    Modules and Packages

  • Connecting Modules

  • $unit and $root

  • Package Import and Export

    Interfaces and SystemTasks

  • Interface with Ports

  • Interface Modports

  • Virtual Interface and Usage

  • System Tasks and Functions

  • SystemVerilog Event Scheduler

    SystemVerilog Classes

  • Creating Class Instances

  • Assign and Copy Class Objects

  • Static Properties and Methods

  • Class Inheritance

  • this and super keywords

  • Local and Protected Properties

  • Overridden Methods and Properties

  • Casting Class Variables

  • Virtual Methods and Polymorphism

  • Virtual Classes

  • Parameterized Classes

Day 3

       Constrained Randomization

  • Random Number Methods

  • Scope and Class Randomizations

  • rand and randc Variables

  • Constraint Block Specifications

  • Set Membership, Distribution, Implication, If-else

  • Randomization of Arrays

  • In-line Constraints

  • In-line Random Variable Control

  • Controlling Random Variables

  • Controlling Constraint Blocks

  • RNG and Manual Seeding

    Functional Coverage

  • Coverage Sampling

  • Coverpoints

  • State and Transition Bins

  • Automatically Generated Bins and Control

  • User-Defined State and Transition Bins

  • Cross Coverage

  • Coverage Options and Computation

    Miscellaneous Topics

  • Overview of SV Assertions

  • Overview of UVM

    Verification Methodologies

  • Proprietary and Standard Methodologies

  • Verification with Verilog, SV and UVM 

  • Using Static and Dynamic Components

  • Pros and Cons of Some Methodologies

  • Choosing Methodologies

  • Discussions and Q&A