Xilinx

Languages

Course Description

This course provides a thorough introduction to SystemVerilog constructs for design. This focus is on:

Writing RTL code using the new constructs available in SystemVerilog
Reviewing new data types, structs, unions, arrays, procedural blocks, re-usable tasks, functions, and packages
Targeting and optimizing Xilinx devices using SystemVerilog.

Duration

2 Days

Level

FPGA 1

Who Should Attend

FPGA designers and logic designers

Course Prerequisites

Verilog design experience or completion of Designing with Verilog

Software Tools

Hardware

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:
Describe the features and benefits of using SystemVerilog for RTL design
Identify the new data types supported in SystemVerilog
Use an enumerated data type for coding a finite state machine (FSM)
Explain how to use structures, unions, and arrays
Describe the new procedural blocks and analyze the affected synthesis results•Define the enhancements and ability to reuse tasks, functions, and packages
Identify how to simplify module definitions and instantiations using interfaces
Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
Target and optimize Xilinx FPGAs by using SystemVerilog
Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
Download a complete SystemVerilog design to an evaluation board

Course Outline

Day 1

Introduction to SystemVerilog Provides an introduction to the SystemVerilog language.
Data Types Describes the data types supported by SystemVerilog.
User-Defined and Enumerated Data Types Describes user-defined and enumerated data types supported by SystemVerilog.
Type Casting Describes type casting in SystemVerilog.
Arrays and Strings Explains the use of arrays in SystemVerilog.
SystemVerilog Building Blocks Describes the design and verification building blocks in SystemVerilog.
Structures Explains the use of structures in SystemVerilog.
Unions Explains the use of unions in SystemVerilog.
Additional Operators in SystemVerilog Describes the operators supported by SystemVerilog beyond those found in Verilog.

Day 2

Procedural Statements Describes the different procedural blocks provided by SystemVerilog.
Control Flow Statements Describes the different control statements provided by SystemVerilog.
Functions Explains the SystemVerilog enhancements to functions.
Tasks Describes the task SystemVerilog construct.
Packages Describes the package SystemVerilog construct.
Interfaces Describes the concept of interfaces in SystemVerilog.
Targeting Xilinx FPGAs Focuses on Xilinx-specific implementation and chip-level optimization.