# Course Description

This course presents SystemVerilog Assertions (SVA) for verification. SVA provides concise
description of functional behavior of designs. Design and verification engineers can use SVA for black-box and white-box verification. SVA can be used for both simulation and formal verification.

# Prerequisites

• Participants must be familiar with Verilog. It will be helpful if participants have some experience in verification.

# Software Tools

Simulator, e.g. from Cadence, Mentor or Synopsys

# Hardware

• Architecture: N/A*

• NA

# Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Explain and deploy the most useful SVA constructs

• Write a broad range of SystemVerilog Assertions

• Use the bind directive to incorporate Assertions into design code at runtime

# Course Outline

Day 1

• SV Assertion Overview

• Black and White Box Verification

• Simulation and Formal Methods

• Immediate and Concurrent Assertions

• Clock and Sampled Values

• Sequence and Property

• Cycle Delay Operator ##N, ##[N:M]

• Sequence Repetition seq[*N]

• Non-consecutive Repetition expr[=N]

• Goto Repetition expr[->N]

• Seq[*M:N], expr[=M:N], expr[->M:N]

• Implication Operators |->, |=>

• Antecedent and Consequent

• Vacuous Success

• Implication and Multiple Matches

• Linear Sequences

• Sequence Operators – or, and, intersect, throughout, within, first_match

• Overlap Sequence ##0

• Property Construct

• Disable assertion disable_iff

• Property Operators – not, or, and, if-else, case, etc

• Concurrent Assertion in Procedural Code

• SVA Clocking Events

• Multi-Clock Sequence and Property

• Clock Flow Rules

• Sampled Value Functions

• Sequence .triggered Method

• Bit Vector Functions

• SVA Local Variables

• SVA Formal Arguments

• Generating Multiple Assertions

• Assertion Binding

• Global and Instance Binding

• SVA Directives – assert, assume, cover, restrict

• SVA Directive Usages

• Simulation vs Formal Usages

• Cover Property and Cover Sequence

• Assume and Restrict for Formal Methods

• Strong and Weak Properties

• Assertion Event Scheduling