MATLAB & Simulink
EMBEDDED SYSTEMS AND FPGA DESIGN
Programming XILINX Zynq SoCs with MATLAB and SIMULINK
Course Highlights
This hands-on, two-day course focuses on developing and configuring models in the Simulink® and deploying on Xilinx®Zynq®-7000 All Programmable SoCs. The course is designed forSimulink users who intend to generate, validate, and deploy embedded code and HDL code for software/hardware codesign using Embedded Coder® and HDL Coder™.
A ZedBoard™ is provided to each attendee for use throughout the course. The board is programmed during the class and is yours to keep after the training.
Topics include:
- Zynq platform overview and environment setup
- Introduction to Embedded Coder and HDL Coder
- IP core generation and deployment
- Using AXI4 Interface
- Processor-in-the-loop verification
- Data interface with real-time application
- integrating device drivers
- Custom referenece design
Partners

Upcoming Program

Techsource Systems is
Mathworks Sole and Authorised Distributor and Training Partner
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Please keep me posted on the next schedule
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Please contact me to arrange customized/ in-house training
Prerequisite
Attended Comprehensive MATLAB and Comprehensive SIMULINK or having equivalent experience in using MATLAB and. Knowledge of C and HDL programming languages.
Course Outline
Day 1 of 1
Zynq Platform Overview and Environment Setup
Objective: Configure Zynq-7000 platform and MATLAB environment.
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Zynq-7000 overview
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Setting up Zynq platform and software
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Configuring MATLAB environment
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Testing connectivity to Zynq hardware
Introduction to Embedded Coder and HDL Coder
Objective: Configure Simulink models for embedded code generation and effectively interpret the generated code.
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Architecture of an embedded application
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Generating ERT code
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Code modules
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Data structures in generated code
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Configuring a Simulink model for HDL code generation
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Using HDL Workflow Advisor
IP Core Generation and Deployment
Objective: Use HDL Workflow Advisor to configure a Simulink model, generate and build both HDL and C code, and deploy to Zynq platform.
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Configuring a subsystem for programmable logic
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Configuring the target interface and peripherals
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Generating the IP core and integrating with SDK
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Building and deploying the FPGA bitstream
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Generating and deploying a software interface model
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Tuning parameters with External Mode
Using AXI4 Interface
Objective: Use various AXI interfaces for data communication between processing system and programmable logic.
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AXI interface overview
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AXI4-Lite applications
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Using AXI4-Stream
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AXI4 performance considerations
Processor-in-the-Loop Verification
Objective: Use processor-in-the-loop to verify the algorithm running on Zynq Platform and profile the execution times in your production algorithm.
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Processor-in-the-loop (PIL) workflow on Zynq
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PIL verification with model reference
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Code execution profiling with PIL
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PIL considerations
Day 2 of 2
Data Interface with Real-Time Application
Objective: Use the UDP interface to stream data between Simulink and real-time application running on Zynq platform.
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Data interface overview
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Configuring UDP blocks for data streaming
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Synchronization data between Simulink and Zynq
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Data interface with AXI Stream
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Design partitioning
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Data interface considerations
Integrating Device Drivers
Objective: Develop device driver interfaces for integrating peripherals on processing system.
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Workflow for developing device drivers
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Using the Legacy Code Tool
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GPIO interface
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Cross-compiling device drivers
Custom Reference Design
Objective: Create and package reusable IP for Vivado and register custom boards and reference designs.
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Motivations for a custom reference design
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Creating reusable IP for Vivado
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Reference design overview
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Customizing a reference design
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Registering board and custom reference design