How to Design a High-Speed Memory Interface

How to Design a High-Speed Memory Interface

SGD 3,000.00

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Course Highlights

This two-days course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs. 

Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.

The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex®-7 FPGA KC705 board.

Who Should Attend

FPGA designers and logic designers

Course Prerequisites

  • VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course

  • Familiarity with logic design: state machines and synchronous design

Very helpful to have:  

        – Basic knowledge of FPGA architecture 

        – Familiarity with Xilinx implementation tools 

       – Familiarity with I/O basics 

       – Familiarity with high-speed I/O standard

Course Benefits

After completing this training, you will know how to:

  • Identify the FPGA resources required for memory interfaces

  • Describe different types of memories

  • Utilize Xilinx tools to generate memory interface designs 

  • Simulate memory interfaces with the Xilinx ISim simulator

  • Implement memory interfaces

  • Identify the board design options for the realization of memory interfaces

  • Test and debug your memory interface design

  • Run basic memory interface signal integrity simulations

For more detail on this course, kindly click here.

Advance payment is required.

Customer shall pay the full amount due fourteen (14) calendar days prior to course commencement or immediately upon placing the Order if placed less than fourteen (14) days and accepted by TechSource, prior to the commencement of the Course(s).

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