Signal Integrity and Board Design for Xilinx FPGAs

Signal Integrity and Board Design for Xilinx FPGAs

SGD 3,600.00
QUANTITY:

Pricing
*For Singapore, prices are subject to prevailing 7% Goods and Services Tax
*Reinstatement fee is subject to changes. Please contact us for latest pricing information

Course Highlights

This 3-days comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.

You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.

Who Should Attend

Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.

Course Prerequisites

  • FPGA design experience preferred (Designing FPGAs Using the
    Vivado Design Suite 1 course or equivalent)
  • Familiarity with high-speed PCB concepts
  • Basic knowledge of digital and analog circuit design
  • Vivado™ tool knowledge is helpful

Course Benefits

After completing this comprehensive training, you will have the necessary skills to:

  • Describe signal integrity effects
  • Predict and overcome signal integrity challenges
  • Simulate signal integrity effects
  • Verify and derive design rules for the board design
  • Apply signal integrity techniques to high-speed interfaces
    between Xilinx FPGAs and semiconductor circuits
  • Plan your board design under FPGA-specific restrictions
  • Supply the FPGAs with power
  • Handle thermal aspects

For more detail on this course, kindly click here.

Advance payment is required.

Customer shall pay the full amount due fourteen (14) calendar days prior to course commencement or immediately upon placing the Order if placed less than fourteen (14) days and accepted by TechSource, prior to the commencement of the Course(s).

Subscribe to our Newsletter