Generating HDL Code from Simulink
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This two-day course shows how to generate and verify HDL code from a Simulink® model using HDL Coder™ and HDL Verifier™.
- Preparing Simulink models for HDL code generation
- Generating HDL code and testbench for a compatible Simulink model
- Performing speed and area optimizations
- Integrating handwritten code and existing IP
- Verifying generated HDL code using testbench and cosimulation
Who Should Attend
Engineers who wish to design and simulate their system with Simulink and accelerate the implemention to FPGA by using HDL Coder.
Signal Processing with Simulink or equivalent experience using Simulink.
Upon the completion of the course, the participants will be able to:
- prepare Simulink models for HDL code generation
- generate HDL code and a test bench for a compatible model
- perform speed and area tradeoffs – interface handwritten code and existing IP
- verify HDL code using a test bench and cosimulation
For more detail on this course, kindly click here.
Advance payment is required.
Customer shall pay the full amount due fourteen (14) calendar days prior to course commencement or immediately upon placing the Order if placed less than fourteen (14) days and accepted by TechSource, prior to the commencement of the Course(s).