Partial Reconfiguration Tools & Techniques
This course demonstrates how to use the Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow. This course also demonstrates how to use thee PR controller and PR decoupler IP in the PR process. You will also gain an understanding of PR implementation in an embedded system environment.
This course covers both the tool flow and mechanics of successfully creating a PR design. This course also covers both UltraScale™ and 7 series architecture design requirements, recommendations, and expectations for PR systems. In addition, it describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications. You will also identify techniques to debug PR designs.
TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products
Who Should Attend
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who want to learn partial reconfiguration techniques
Essentials of FPGA Design course
Vivado Design Suite Static Timing Analysis and Xilinx Design Constraints course
Advanced Tools and Techniques of the Vivado Design Suite course
Working HDL knowledge (VHDL or Verilog)
Vivado Design or System Edition with PR license
Architecture: UltraScale and 7 series FPGAs
Demo board: Kintex® UltraScale FPGA KCU105 board, Kintex-7 FPGA KC705 board, and ZedBoard**
After completing this comprehensive training, you will know how to:
Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices)
Define PR regions and reconfigurable modules with the Vivado Design Suite
Generate the appropriate full and partial bitstreams for a PR Design
use the ICAP and PCAP components to deliver the Partially Reconfigurable systems
Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers, and MGTs
Implement a Partial Reconfiguration system using the following techniques:
Direct JTAG connection
Timing constraints and analysis
Implement a PR system using the PRC IP
Implement a PR system in an embedded environment
Debug PR designs
1.1 Partial Reconfiguration Methodology
1.2 Demo: Introduction to Partial Reconfiguration
1.3 Partial Reconfiguration Tool Flow
1.4 Lab 1: Partial Reconfiguration Flow
Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
1.5 Lab 2: Floorplanning the PR Design
Illustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock.
1.6 Optional: FPGA Configuration Overview
1.7 Demo: Partial Reconfiguration Controller (PRC) IP
1.8 Partial Reconfiguration Design Recommendations
2.0 Lab 3: Using the Partial Reconfiguration Controller in a PR Design
Illustrates using the PRC IP and hardware triggers to manage partial bitstreams.
2.1 Managing Clocks, I/Os, and GTs
2.2 Partial Reconfiguation: Managing Timing
2.3Lab 4: Partial Reconfiguration Timing Analysis and Constraints
Shows how area groups and Reconfigurable Partitions affect design performance.
2.4 Partial Reconfiguration in Embedded Systems
2.5 Lab 5: Partial Reconfiguration in Embedded Systems
Illustrates implementing PR designs in an embedded environment.
2.6 Debugging Partial Reconfiguration Designs
2.7 Lab 6: Debugging a Partial Reconfiguration Design
Demonstrates using ILA cores to debug PR designs and shows which signals to monitor during debugging.
2.8 Partial Reconfiguration Design Recommendations
2.9 PCIe Core and Partial Reconfiguration