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Applying Signal and Image Processing with Vitis Model Composer, MATLAB and Simulink (New)
Must-to-Attend for Intermediate Users
Applying Signal and Image Processing with Vitis Model Composer, MATLAB and Simulink
Learn core Model-based Designs for HDL, HLS and AI Engine
Complimentary Services: Post training email support & 1-hr consultation session within 1 month after the course completion!
Course
Highlights
This three-days hands-on training will provide experience in applying Signal and Image Processing with the Vitis Model Composer tool for model-based designs.
The course provides experience with:
- Working on variety of filter techniques with emphasis on optimal implementation in AMD Xilinx devices followed by examination of FFTs, Video and Image Processing
- Creating a model-based design using HDL, HLS, and AIE library blocks along with custom blocks in Vitis Model Composer
- Implementing DSP functions using Vitis Model Composer
- Utilizing design implementation tools
- Transforming algorithmic specifications to production-quality IP implementations using automatic optimizations and leveraging the high-level synthesis technology of the Vitis HLS tool
- Creating Versal® AI Engine graphs and kernels using Vitis Model Composer
- Connecting AI Engine blocks and non-AI Engine blocks
- Verifying and debugging AI Engine code using the Vitis analyzer
- Simulating and debugging a complex system created using AI Engine library blocks
Who Should
Attend
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing Versal AI Engine, HDL and HLS algorithms using the MathWorks MATLAB® and Simulink® software and want to use Vitis Model Composer.
Course
Prerequisites
- Basic experience with the MATLAB and Simulink software
- Basic understanding of DSP designs and sampling theory
- Comfort with the C/C++ programming language for HLS or AI Engine model designs
Course
Benefits
Upon the completion of the course, the participants will be able to:
- Utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
- Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
- Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
- Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
- Explain the algorithms for video and imaging systems and their implementations in FPGAs
- Use optimized HDL, HLS, and AI Engine blocks directly from the Simulink tool library browser
- Create, simulate, and debug a Vitis Model Composer design in the Simulink Environment using HDL, HLS, and AIE block libraries
- Perform co-simulation and hardware verification
- Use DSP blocks in Vitis Model Composer to implement DSP functions
- Implement multi-rate systems in Vitis Model Composer
- Design a processor-controllable interface using Vitis Model Composer
- Generate Ips from C-based design sources using the Vitis HLS tool for se in the Vitis Model Composer environment
- Import custom HDL, HLS and AI Engines code as blocks into Vitis Model Composer
- Generate output products using automatic code generation
- Connect AI Engine blocks and non-AI Engine blocks
- Perform AI Engine code verification using the Vitis analyzer
- Create, simulate, and debug a complex system created using AI Engine library blocks
Partners
Upcoming Program
- Please keep me posted on the next schedule
- Please contact me to arrange customized/ in-house training
Course Outline
Back to Basics
- FPGA Architecture
- FPGA Math
- Lab: Signed number conversion, quantization and rounding, adders, subtracters, and accumulation.
Learn how to estimate device resource utilization for basic math functions. Compare different methodologies for implementing functions. - Shift Registers, RAM, and Applications
Discuss memory structures in FPGAs, including registers, distributed memory, block RAM, and SRL32. Examine concatenation and other uses of these elements. - Lab: SRL32E and RAM implementations.
Learn how to estimate device resource utilization for basic math functions. Compare different methodologies for implementing functions.
Filters
- The FIR Filter
- Lab: Filter implementation and resource and performance estimation.
- Advanced Filter Techniques
- Lab: Filter Implementations, Resource and Performance Estimation
Advanced filter topologies are studied. Architect multichannel and multirate filters using various methods. Implementation strategies will be discussed, and optimal methods used. - The Fast Fourier Transform
- Lab: FFT implementation and resource and performance estimation.
Select correct parameters for FFT implementations to meet design targets. Resource estimation will be studied and trade-offs with performance examined through implementation examples
Video and Imaging
- Video and Imaging
- Where Do We Go from Here?
- Demonstration: System Generator and the CORE Generator™ Tool with a DSP-Targeted Reference Design
- Where Can I Learn More?
Introduction to Vitis Model Composer
- Introduction to Vitis Model Composer
Introduces the Vitis Model Composer tool and describe the optimized HDL, HLS, and AI Engine library blocks available in Vitis Model Composer. - Basics of the Simulink Environment
Describes the Simulink software environment, some of the commonly used signal source and sink blocks available in the Simulink software, and how hierarchical designs are created and protected using masked subsystems.
Vitis Model Composer for HDL
- HDL Library in Vitis Model Composer
Illustrates how the HDL library can be used in Vitis Model Composer and how to analyze performance and resource usage in Vitis Model Composer. - HDL Library Compilation and Hardware Co-Simulation
Covers how to import HDL modules as well as perform HDL co-simulation and hardware verification. Reviews the compilation types for Vitis Model Composer designs. Also introduces Super Sample Rate (SSR) blocks in Vitis Model Composer. - DSP Blocks in Vitis Model Composer
Describes the DSP blocks in the HDL and AI Engine library. Also reviews the basics of AXI4 interfaces. - Working with Filter Designs
Describes the concept of designing filters supported by Vitis Model Composer. - Working with Multi-Rate Systems
Explains how a multi-rate DSP system uses multiple sampling rates within a system.
Vitis Model Composer for HLS
- HLS Library in Vitis Model Composer
Describes how create Vitis Model Composer designs using HLS block libraries, import C/C++ code into Vitis Model Composer, and generate output products using automatic code generation.
Vitis Model Composer for AI Engines
- AI Engine Library in Vitis Model Composer
Demonstrates the usage the AI Engine library in Vitis Model composer for creating an AI Engine design, which involves preparing the kernel and importing the AI Engine code as a block. - AI Engine Simulation and Code Generation
Illustrates the process of generating AI Engine code with a data flow graph, which involves Simulink simulation with the AI Engine library for functional verification. Also describe the hardware validation flow through generating a hardware image targeting a specific platform for the Simulink environment. - Connecting AI Engine and Non-AI Engine Blocks
Explains how to interconnect AI Engine blocks and non-AI Engine (HDL and HLS) blocks. - Debugging an AI Engine Design in Vitis Model Composer
Shows how to use the Vitis analyzer for viewing and analyzing various parameters that are useful for debugging Versal AI Engines.
GitHub Examples
- Exploring Vitis Model Composer Examples in GitHub
Introduces different categories of Vitis Model Composer examples in GitHub and describes the methods to access these examples from GitHub.
