High-Level Synthesis with the Vitis HLS Tool

Enhance productivity using the Vitis HLS tool

TechSource Systems Pte Ltd

Course
Highlights

This two-day course provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) tool.
The focus of this course is on:

  • Converting C/C++ designs into RTL implementations
  • Learning the Vitis HLS tool flow
  • Creating I/O interfaces for designs by using the Vitis HLS tool
  • Applying different optimization techniques
  • improving throughput, area, latency, and logic by using different HLS pragmas/directives
  • Exporting IP that can be used with the Vivado® IP catalog
  • Downloading for in-circuit validation

What’s New for 2021.2

  • Ease-of-use (EoU) enhancements
    • Analysis and reporting enhancements
    • Timing and QoR enhancements
  • Support for the new Timeline Trace Viewer after simulation which shows the runtime profile of the design and allows the user to remain in the Vitis HLS GUI
  • All labs have been updated to the latest software versions
TechSource Systems Pte Ltd

Who Should
Attend

Software and hardware engineers looking to utilize high-level synthesis

TechSource Systems Pte Ltd

Course
Prerequisites

  • C or C++ knowledge
  • Basic RTL design flow knowledge
TechSource Systems Pte Ltd

Course
Benefits

After completing this comprehensive training, you will have the
necessary skills to:

  • Enhance productivity using the Vitis HLS tool
  • Describe the high-level synthesis flow
  • Use the Vitis HLS tool for a first project
  • Identify the importance of the test bench
  • Use directives to improve performance and area and select RTL interfaces
  • Identify common coding pitfalls as well as methods for improving code for RTL/hardware
  • Perform system-level integration of IP generated by the Vitis HLS tool

Partners

TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Course Outline

Introduction to High-Level Synthesis

Objective: Overview of high-level synthesis (HLS), the Vitis HLS tool flow, and the verification advantage. Describe the need for high-level synthesis. Explore the Vitis™ HLS tool flow. Identify the steps to extract RTL from C using the Vitis HLS tool.

  • The need for high-level synthesis
  • Vitis™ HLS tool flow
  • Steps to extract RTL from C using the Vitis HLS tool
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Vitis HLS Tool Flow

Objective: Explore the basics of high-level synthesis and the Vitis HLS tool. Identify the steps to extract RTL from C using the Vitis™ HLS tool. Describe the basic terminology used in HLS. Perform C language support for the Vitis HLS tool. Describe the C validation and RTL Verification process in the Vitis HLS tool.

  • Steps to extract RTL from C using the Vitis™ HLS tool
  • Basic terminology used in HLS
  • C language support for the Vitis HLS tool
  • C validation and RTL Verification process in the Vitis HLS tool

Design Exploration with Directives

Objective: Explore different optimization techniques that can improve the design performance.

  • Impact from directives to the performance and area objectives of a C design
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Vitis HLS Tool Command Line Interface

Objective: Describe the Vitis HLS tool flow in command prompt mode. Use the Vitis™ HLS tool command line interface. Use commands to create the project and solution. Use commands to perform simulation, synthesis, and C/RTL co-simulation and export the design as an IP block. Describe the interoperability between the Vitis HLS tool command line interface and GUI.

  • Vitis™ HLS tool command line interface
  • Commands to create the project and solution
  • Interoperability between the Vitis HLS tool command line interface and GUI
  • Commands to perform simulation, synthesis, and C/RTL co-simulation and export the design as an IP block

Introduction to Vitis HLS Methodology

Objective: Introduce the methodology guidelines covered in this course and the HLS Design Methodology steps. Describe the HLS Design Methodology steps. Describe the set of best practices when creating designs based on C/C++.

  • HLS Design Methodology steps
  • Best practices when creating designs based on C/C++
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Introduction to I/O Interfaces

Objective: Explain interfaces such as the block-level and port-level protocols abstracted by the Vitis HLS tool from the C design. List the types of I/O abstracted in the Vitis™ HLS tool. Distinguish between block-level and port-level I/O protocols.

  • Types of I/O abstracted in the Vitis™ HLS tool
  • Block-level versus port-level I/O protocols

Block-Level Protocols

Objective: Explain the different types of block-level protocols abstracted by the Vitis HLS tool. List the types of block-level protocols abstracted in the Vitis™ HLS tool.

  • Types of block-level protocols abstracted in the Vitis™ HLS tool
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Port-Level I/O Protocols

Objective: Describe the port-level interface protocols abstracted by the Vitis HLS tool from the C design. List the types of port-level protocols abstracted in the Vitis™ HLS tool.

  • Types of port-level protocols abstracted in the Vitis™ HLS tool

AXI Adapter Interface Protocols

Objective: Explain the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave), and AXI4-Stream) supported by the Vitis HLS tool. Describe how AXI adapter interface protocols are implemented.

  • AXI adapter interface protocols
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Port-Level I/O Protocols: Memory Interfaces

Objective: Describe the memory interface port-level protocols (such as block RAM and FIFO) abstracted by the Vitis HLS tool from the C design. Explain how memory interface port-level interfaces protocols are implemented. Describe how pointer interfaces are implemented.

  • Memory interface port-level interfaces protocols
  • Pointer interfaces

Pipeline for Performance: PIPELINE

Objective: Describe the PIPELINE directive for improving the throughput of a design. Describe the pipelining technique that improves throughput of a design or reduces the initiation interval. Identify some of the bottlenecks that can impact design performance.

  • Pipelining technique
  • Bottlenecks that can impact design performance
TechSource Systems Pte Ltd

Pipeline for Performance: DATAFLOW

Objective: Describe the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible. Describe the dataflow technique that improves the throughput of a design. Identify some of the bottlenecks that impact design performance.

  • Dataflow technique for throughput
  • Bottlenecks that impact design performance
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Optimizing for Throughput

Objective: Identify the performance limitations caused by arrays in your design. Explore optimization techniques to handle arrays for improving performance.

  • Performance Limitation of Arrays in C
  • Technique to optimize array performance

Optimizing for Latency: Default Behavior

Objective: Describe the default behavior of the Vitis HLS tool on latency and throughput.

  • Default implementations of loops and functions by the Vitis™ HLS tool
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Optimizing for Latency: Reducing Latency

Objective: Describe the default behavior of the Vitis HLS tool on latency and throughput.

  • Default implementations of loops
  • Loops to achieve the desired latency and throughput

Optimizing for Area and Logic

Objective: Describe different methods for improving resource utilization and explains how some of the directives have impact on the area utilization.

  • Methods for improving resource utilization
  • Structure of the design by using directives to improve the area
  • Arbitrary precision types for optimal resource usage
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Migrating to the Vitis HLS Tool

Objective: Review key considerations when moving from the Vivado HLS tool to the Vitis HLS tool.

  • Key factors when migrating from the Vivado® HLS tool to the Vitis™ HLS tool

HLS Design Flow – System Integration

Objective: Describe the traditional RTL flow versus the Vitis HLS tool design flow.

  • Improve productivity by using a high-level language for a hardware design
  • Traditional HDL design flow versus a C-based design flow
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Vitis HLS Tool C++ Libraries: Arbitrary Precision

Objective: Describe Vitis HLS tool support for the C/C++ languages as well as arbitrary precision data types.

  • Support offered by the Vitis™ HLS tool for C++
  • Bit-accurate operators using arbitrary precision types

Hardware Modeling

Objective: Describe hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class.

  • Efficient hardware from C sources using streams and the shift register class
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Using Pointers in the Vitis HLS Tool

Objective: Explain the use of pointers in the design and workarounds for some of the limitations.

  • Modeling issues present when using pointers
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