FPGAs Implementation with Simulink and System Generator

Develop Signal Processing algorithm for FPGA device using Simulink and the Xilinx System Generator.

TechSource Systems Pte Ltd

Course
Highlights

This is a three-day training class that provides system architects, DSP designers, and FPGA designers a hands-on course covering how to develop signal processing algorithm for FPGA device using Simulink and the Xilinx design flow for developing and implementing advanced and low-cost Digital Signal Processing design using System Generator.

You will learn how to:

  • Use Simulink to perform system-level DSP design
  • Approach the complexities of high-performance DSP design
  • Implement a design from algorithm concept to hardware verification using Xilinx automatic translation (System Generator) and implementation (Vivado) tools
TechSource Systems Pte Ltd

Who Should
Attend

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB® and Simulink® software and want to use Xilinx System Generator for DSP design.

TechSource Systems Pte Ltd

Course
Prerequisites

  • Experience with the MATLAB and Simulink software
  • Basic understanding of sampling theory
TechSource Systems Pte Ltd

Course
Benefits

After completing this comprehensive training, you will have the necessary skills to:

  • Use Simulink to perform system-level DSP design
  • Approach the complexities of high-performance DSP design
  • Describe the System Generator design flow for implementing DSP functions
  • Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation
  • List various low-level and high-level functional blocks available in System Generator
  • Run hardware co-simulation
  • Identify the high-level blocks available for FIR and FFT designs
  • Implement multi-rate systems in System Generator
  • Integrate System Generator models into the Vivado IDE
  • Design a processor-controllable interface using System Generator for DSP
  • Generate IPs from C-based design sources using the Vitis HLS tool for use in the System Generator environment
  • Create and simulate designs using Model Composer

Partners

TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Course Outline

What is Simulink?

Objective: Get an introduction to Simulink.

  • What is Simulink?
  • Benefits of using Simulink
  • Simulink add-ons
  • A look at a Simulink model
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Creating and Simulating a Model

Objective: Explore the Simulink interface and block libraries. Build a simple model and analyze the simulation results.

  • Creating and editing a Simulink model
  • Defining system inputs and outputs
  • Simulating the model and analyzing results

Modeling Discrete Dynamic Systems

Objective: Model discrete dynamic systems, and visualize frame-based signals and multichannel signals using a scope.

  • Modeling a discrete system with basic blocks
  • Finding sample times of block outputs
  • Using frames in your model
  • Using buffers
  • Frames vs. multichannel signals
  • Viewing frame-based signals
  • Behavior of delay blocks with frame-based signals
  • Multichannel frame-based signals
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Spectral Analysis

Objective: Perform spectral analysis in the Simulink environment, and use spectrum computation in an algorithm.

  • Performing spectral analysis with the Spectrum Scope block
  • Choosing spectral analysis parameters
  • Analyzing power spectrum of a motor noise
  • Building a spectral classifier of speech
  • Determining the frequency response of a discrete system

Introduction to System Generator

Objective: explains why there is a need for an integrated flow from system design to implementation and provides an overview of System Generator and the tools with which it interfaces.

  • Overview of the MATLAB and Simulink Software and System Generator
  • System Generator Design Flow
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Simulink Software Basics

Objective: describes the Simulink® software environment, some of the commonly used signal sources available in the Simulink software to provide stimulus to a model, some of the commonly used sink blocks available in the Simulink software to view the output of a model, and how hierarchical designs are created.

  • Simulink and MATLAB Software
  • Stimulus and Response
  • Sample Period and Solvers
  • Workspace
  • Design Hierarchy and Masked Subsystems
  • Lab 1: Using the Simulink Software

Basic Xilinx Design Capture

Objective: describes various blocksets available in System Generator, how signals are fed to and results are read from a System Generator-based design. It also reviews various data types that are supported by System Generator, the steps involved in performing HDL co-simulation and hardware verification, and how hardware verification is beneficial for complex system designs.

  • Gateway In and Gateway Out
  • Data Types
  • Constructing a Design Using Xilinx Design Capture
  • System Generator Block
  • HDL Co-Simulation
  • Hardware Verification
  • Xilinx SSR Blockset
  • Demo: System Generator Gateway Blocks
  • Lab 2: Getting Started with Xilinx System Generator
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Signal Routing

Objective: covers how signals are converted through Gateway In blocks. It also describes the supporting blocks for routing signals as well as the blocks.

  • Signal Conversion
  • Bit Picking
  • BitBasher Block
  • Expression Block
  • Lab 3: Signal Routing

Implementing System Control

Objective: describes the control mechanisms available in System Generator, the available blocks located in System Generator for controlling data movement, and the methods for designing state machines. It also describes how to distinguish between valid and invalid data.

  • Control Mechanisms
  • Handling Data Bursts
  • MCode Block
  • Lab 4: Implementing System Control
TechSource Systems Pte Ltd

Multi-Rate Systems

Objective: reviews the definition of multi-channel and multi-rate systems and describes sample rate-changing blocks, Simulink® software propagation rules, and the hardware realization for rate-changing blocks.

  • Sample Rate-Changing Blocks
  • Simulink Software Propagation Rules
  • Hardware
  • Lab 5: Designing a MAC-Based FIR
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Filter Design

Objective: describes the various filters supported in System Generator. It also covers FIR Compiler block filter implementation, integration of the Filter Design and Analysis Tool (FDATool) block in System Generator, and hardware oversampling.

  • MAC FIR Filters
  • FIR Compiler
  • FDATool
  • Lab 6: Designing a FIR Filter Using the FIR Compiler Block

System Generator, Vivado Design Suite, and Vitis HLS Integration

Objective: describes the Xilinx tool flows among System Generator, the Vivado® IDE, and the Vitis HLS tool.

  • System Generator, Vivado Design Suite, and Vitis HLS Integration
  • Vivado IP Integrator and System Generator
  • Vitis HLS and System Generator Integration
  • Lab 7: System Generator and Vivado IDE Integration
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

DSP Platforms

Objective: provides overview of the DSP kits targeting development board platforms. It also highlights some important design techniques related specifically to the reference designs included in the kits.

  • DSP Targeted Design Platform (TDP)
  • AXI4 Protocol Overview
  • DSP TDP Reference Design Overview
  • Lab 8: System Generator and Vitis HLS Tool Integration
  • Lab 9: AXI4-Lite Interface Synthesis

Introduction to Model Composer

Objective: explains why there is a need for an integrated flow from system design to implementation and how the gap between high-level algorithm developers and low-level RTL designers can be reduced. It provides an overview of Model Composer and the tools with which it interfaces.

  • Explain what Model Composer is and the motivation behind using it
  • Use the Xilinx-optimized blocks available in Model Composer
  • Describe the system design flow using Model Composer
  • Simulate and verify the design using Model Composer
  • Demo: Introduction to Model Composer
TechSource Systems Pte Ltd
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