TechSource Systems is MathWorks Authorised Reseller and Training Partner
Develop Signal Processing algorithm for FPGA device using Simulink and the Xilinx System Generator.
This is a three-day training class that provides system architects, DSP designers, and FPGA designers a hands-on course covering how to develop signal processing algorithm for FPGA device using Simulink and the Xilinx design flow for developing and implementing advanced and low-cost Digital Signal Processing design using System Generator.
You will learn how to:
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB® and Simulink® software and want to use Xilinx System Generator for DSP design.
After completing this comprehensive training, you will have the necessary skills to:
Objective: Get an introduction to Simulink.
Objective: Explore the Simulink interface and block libraries. Build a simple model and analyze the simulation results.
Objective: Model discrete dynamic systems, and visualize frame-based signals and multichannel signals using a scope.
Objective: Perform spectral analysis in the Simulink environment, and use spectrum computation in an algorithm.
Objective: explains why there is a need for an integrated flow from system design to implementation and provides an overview of System Generator and the tools with which it interfaces.
Objective: describes the Simulink® software environment, some of the commonly used signal sources available in the Simulink software to provide stimulus to a model, some of the commonly used sink blocks available in the Simulink software to view the output of a model, and how hierarchical designs are created.
Objective: describes various blocksets available in System Generator, how signals are fed to and results are read from a System Generator-based design. It also reviews various data types that are supported by System Generator, the steps involved in performing HDL co-simulation and hardware verification, and how hardware verification is beneficial for complex system designs.
Objective: covers how signals are converted through Gateway In blocks. It also describes the supporting blocks for routing signals as well as the blocks.
Objective: describes the control mechanisms available in System Generator, the available blocks located in System Generator for controlling data movement, and the methods for designing state machines. It also describes how to distinguish between valid and invalid data.
Objective: reviews the definition of multi-channel and multi-rate systems and describes sample rate-changing blocks, Simulink® software propagation rules, and the hardware realization for rate-changing blocks.
Objective: describes the various filters supported in System Generator. It also covers FIR Compiler block filter implementation, integration of the Filter Design and Analysis Tool (FDATool) block in System Generator, and hardware oversampling.
Objective: describes the Xilinx tool flows among System Generator, the Vivado® IDE, and the Vitis HLS tool.
Objective: provides overview of the DSP kits targeting development board platforms. It also highlights some important design techniques related specifically to the reference designs included in the kits.
Objective: explains why there is a need for an integrated flow from system design to implementation and how the gap between high-level algorithm developers and low-level RTL designers can be reduced. It provides an overview of Model Composer and the tools with which it interfaces.