Designing with the Ultrascale and Ultrascale+ Architectures

The UltraScale™ and UltraScale+™ architectures to both new and experienced designers.

TechSource Systems Pte Ltd

Course
Highlights

This course introduces the UltraScale™ and UltraScale+™
architectures to both new and experienced designers.

The emphasis is on:

  • Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
  • Describing improvements to the dedicated transceivers and
    Transceiver Wizard
  • Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
  • Migrating existing designs and IP to the UltraScale architecture
    with optimal use of the Vivado® Design Suite

What’s New for 2021.2

  • All labs have been updated to the latest software versions
TechSource Systems Pte Ltd

Who Should
Attend

Anyone who would like to build a design for the UltraScale or UltraScale+ device family.

TechSource Systems Pte Ltd

Course
Prerequisites

  • Designing FPGAs Using the Vivado Design Suite 1 course
  • Intermediate VHDL or Verilog knowledge
TechSource Systems Pte Ltd

Course
Benefits

After completing this comprehensive training, you will have the
necessary skills to:

  • Take advantage of the primary UltraScale architecture resources
  • Describe the new CLB capabilities and the impact that they make on your HDL coding style
  • Define the block RAM, FIFO, and DSP resources available
  • Describe the new type of memory structures available in UltraScale+™ devices, such as UltraRAM and the high bandwidth
    memory (HBM) available in Virtex® UltraScale+ devices
  • Properly design for the I/O and SERDES resources
  • Identify the MMCM, PLL, and clock routing resources included
  • Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces
  • Describe the additional features of the dedicated transceivers
  • Effectively migrate your IP and design to the UltraScale
    architecture as quickly as possible

Partners

TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

TechSource Systems is MathWorks Authorised Reseller and Training Partner

Upcoming Program

  • Please keep me posted on the next schedule
  • Please contact me to arrange customized/ in-house training

Course Outline

Introduction to the UltraScale Architecture

Objective: Review the UltraScale architecture, which includes enhanced CLB resources, DSP resources, etc.

  • Primary differences between the 7 series and UltraScale™ FPGA architectures
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

UltraScale Architecture CLB Resources

Objective: Examine the CLB resources, such as the LUT and the dedicated carry chain, in the UltraScale architecture.

  • CLB layout and interconnect found in the UltraScale™ architecture
  • The use of control signals (sets, resets, and clock enables)

HDL Coding Techniques

Objective: Cover basic digital coding guidelines used in an FPGA design.

  • The use of control signals (sets, resets, and clock enables)
  • Benefits of following Xilinx recommendations on resets
  • Difference between inference and instantiation
  • Infer the dedicated hardware resources
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

UltraScale Architecture Clocking Resources

Objective: Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks.

  • Clocking architecture and available resources in the UltraScale™ architecture
  • Clocking architectures of 7 series versus UltraScale FPGAs

FPGA Design Migration

Objective: Migrate an existing 7 series design to the UltraScale architecture.

  • Limitations of the Vivado® Design Suite and its ability to synthesize for the new UltraScale architecture resources
  • The limitations of the Vivado Design Suite to migrate IP that was built for 7 series FPGAs
  • Consistent methodology for migrating 7 series designs to the UltraScale architecture
  • Lab: Clocking Migration
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

UltraScale Architecture Block RAM Memory Resources

Objective: Review the block RAM resources in the UltraScale architecture.

  • Dedicated block RAM memory resources in the UltraScale™ architecture
  • Different modes available in block RAM memory

UltraScale Architecture FIFO Memory Resources

Objective: Review the FIFO resources in the UltraScale architecture.

  • Capabilities of the built-in FIFO in UltraScale™ devices
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

UltraRAM Memory

Objective: Use UltraRAM for a design requiring a larger memory size than block RAM.

  • Features of UltraRAM
  • Differences between block RAM and UltraRAM

High Bandwidth Memory

Objective: Use high bandwidth memory (HBM) for applications requiring high bandwidth.

  • Features of Xilinx high bandwidth memory (HBM)
  • Differences between HBM and other available memory types
  • Organization of HBM memory in Virtex® UltraScale+™ FPGAs
  • Features of the AXI HBM Memory Controller IP core
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UltraScale Architecture DSP Resources

Objective: Review the DSP resources in the UltraScale architecture.

  • DSP slice architecture in the UltraScale™ architecture
  • Capabilities of DSP slice resources
  • Instantiate and infer DSP resources
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Design Migration Software Recommendations

Objective: List the Xilinx software recommendations for design migrations from 7 series to the UltraScale architecture.

  • Properly migrating your physical and timing constraints from 7 series to UltraScale™ FPGAs
  • Capabilities of the Vivado® Design Suite to manage your design’s high fanout signals
  • Lab: DDR3 MIG Design Migration
  • Lab: DDR4 Design Creation Using MIG

UltraScale Architecture I/O Resources: Overview

Objective: Review the I/O resources in the UltraScale architecture.

  • The I/O resources available in UltraScale™ FPGAs
  • Different types of I/O banks
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

UltraScale Architecture I/O Resources: Component Mode

Objective: Implement a high-performance, source-synchronous interface using I/O resources in Component mode for the UltraScale architecture.

  • Component mode of each block in the IOB
  • SelectIO™ interface logic and SERDES technology in component mode
  • Programmable delay lines for inputs and outputs

UltraScale Architecture I/O Resources: Native Mode

Objective: Implement a high-performance, source-synchronous interface using I/O resources in Native mode for the UltraScale
architecture.

  • SelectIO™ interface logic and BITSLICE technology in native mode
  • Native mode clocking
  • High Speed SelectIO Wizard
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

Design Migration Methodology

Objective: Review the migration methodology recommended by Xilinx for design migrations.

  • Existing 7 series design to the UltraScale™ architecture
  • Recommended IP migration methodology
  • Use beneficial Vivado® Design Suite utilities and reports to migrate the designs to UltraScale FPGAs
  • Lab: 10G PCS/PMA and MAC Design Migration

UltraScale Architecture Transceivers

Objective: Review the enhanced features of the transceivers in the UltraScale architecture.

  • When to use each type of serial transceiver
  • New features and clocking options of the serial transceivers in the UltraScale™ architecture
TechSource Systems Pte Ltd
TechSource Systems Pte Ltd

UltraScale FPGAs Transceivers Wizard

Objective: Use the Transceivers Wizard to build a design that uses a single serial transceiver and observe the created file structures.

  • UltraScale™ Transceiver Wizard to customize the GTs in your design

Introduction to the UltraScale+ Families

Objective: Identify the enhancements made to the UltraScale architecture in the UltraScale+ architecture families.

  • The features of UltraScale+™ architecture
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