Overview

​

FPGAs and Programmable SoCs are evolving with very large capacity and improved performance. Designing with these platforms needs efficient and productive approaches.

​

Using High Level Design approaches such as High Level Synthesis (C/C++ to RTL), MATLAB/Simulink, System Generator, Model Composer and System Level compilers are introduced in this session. 

This live webinar is presented by our Principal Consultant and Trainer specialised in FPGA.

​

Skill Gained

​

Get an overview of High Level design approaches with various tools like Xilinx High Level Synthesis, MATLAB/Simulink, System Generator, Model Composer that can benefit your design process.

​

Speaker Profile

Wikneswaran (Wicky) Pillai  

Principal Consultant and Trainer

​

Wicky is an experienced FPGA designer with over 22 years of experience in applications of FPGAs and related methodologies to the emerging programmable logic industry. He has delivered numerous FPGA design consultancy services and conducting several trainings in FPGAs and HDL based methodologies for international companies like Cisco Systems, Tata Communications, Olympus, DSO National Laboratories, ST Electronics, etc.

​

Prior to that, he has headed a team primarily focusing on FPGA centric designs and has done architecting of key FPGA based systems and defining optimal engineering processes.

Related Webinars

• MATLAB and Simulink Made Easy for FPGA Design

​

• How to Shift ASIC and FPGA Verification Left Using MATLAB and Simulink

​

• Next generation Cloud and Edge Machine Learning solutions from Xilinx - An Overview

​

• Systematic Timing Closure techniques for Xilinx FPGA Designs