MATLAB & Simulink

EMBEDDED SYSTEMS AND FPGA DESIGN

Generating HDL Code from SIMULINK

Course Highlights

This two-day course shows how to generate and verify HDL code from a Simulink® model using HDL Coder™ and HDL Verifier™.  

Topics include:

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• Preparing Simulink models for HDL code generation

• Generating HDL code and testbench for a compatible Simulink model

• Performing speed and area optimizations

• Integrating handwritten code and existing IP

• Verifying generated HDL code using testbench and cosimulation

Who Should Attend 

Engineers who wish to design and simulate their system with Simulink and accelerate the implemention to FPGA by using HDL Coder. 

Techsource Systems is
Mathworks Sole and Authorised Distributor and Training Partner

• Please keep me posted on the next schedule 

• Please contact me to arrange customized/ in-house training
   

Course Benefits

Upon the completion of the course, the participants will be able to

- prepare Simulink models for HDL code generation

- generate HDL code and a test bench for a compatible model

- perform speed and area tradeoffs - interface handwritten code and existing IP

- verify HDL code using a test bench and cosimulation 

Prerequisite

MATLAB Fundamentals, Simulink for System and Algorithm Modeling 

Course Outline

Day 1 of 2

Preparing Simulink models for HDL code generation

Objective: Prepare a Simulink model for HDL code generation. Generate HDL code and testbench for simple models requiring no optimization.

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• Preparing Simulink Models for HDL Code Generation

• Generating HDL code

• Generating a test bench

• Verifying generated HDL code with an HDL simulator

Fixed-Point Precision Control

Objective: Establish correspondence between generated HDL code and specific Simulink blocks in the model. Use Fixed-Point Tool to finalize fixed point architecture of the model.

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• Fixed-point scaling and inheritance

• Fixed-Point Desinger workflow

• Fixed-Point Tool

• Command-line interface

Generating HDL Code for Multirate Models

Objective: Generate HDL code for multirate designs.

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• Preparing a multirate model for generating HDL code

• Generating HDL code with single or multiple clock pins

• Understanding and applying techniques used for clock domain crossing

Day 2 of 2

Optimizing Generated HDL Code

Objective: Use pipelines to meet design timing requirements. Use specific hardware implementations and share resources for area optimization.

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• Generating HDL code with the HDL Workflow Advisor

• Meeting timing requirements via pipelining

• Choosing specific hardware implementations for compatible Simulink blocks

• Sharing FPGA/ASIC resources in subsystems

• Verifying that the optimized HDL code is bit-true cycle-accurate

• Mapping Simulink blocks to dedicated hardware resources on FPGA 

Using Native Floating Point

Objective: Implement floating point values and operations in your HDL code.

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• Why and when to use native floating point

• Target-independent HDL code generation with HDL Coder 

• Fixed-point vs. floating point comparison

• Optimizing floating point implementations

Interfacing External HDL Code with Generated HDL

Objective: Incorporate hand-written HDL code and/or vendor party IP in your design.

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• Interfacing external HDL code

Verifying HDL Code with Cosimulation

Objective: Verify your HDL code using an HDL simulator in the Simulink model.

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• Verifying HDL code generated with HDL Coder 

• Comparing manually written HDL code with a "golden model" 

• Incorporating HDL code into Simulink for simulation