Xilinx

DSP Design

FPGA Implementation with Simulink and System Generator

Course Highlights

This is a three-day training class that provides system architects, DSP designers, and FPGA designers a hands-on course covering how to develop signal processing algorithm for FPGA device using Simulink and the Xilinx design flow for developing and implementing advanced and low-cost Digital Signal Processing design using System Generator.

 

You will learn how to:

  • Use Simulink to perform system-level DSP design

  • Approach the complexities of high-performance DSP design

  • Implement a design from algorithm concept to hardware verification using Xilinx automatic translation (System Generator) and implementation (Vivado) tools

Partners 

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products

Upcoming Program

Prerequisities

Attended "Comprehensive MATLAB" and "Comprehensive SIMULINK", or equivalent experience using MATLAB & SIMULINK. Participants are expected to have some exposure to signal processing techniques and knowledge of Xilinx FPGA fundamentals.

 

Although the course includes some very basic revision of some DSP algorithms, it is expected that you understand the basics of digital signal processing theory for functions such as:

 

  • FIR (Finite Impulse Response)

  • Oscillators and Mixers

  • FFT (Fast Fourier Transform) algorithm and equalizer

Duration

3 Days

Software Tools

  • Vivado® Design Suite System Edition 2018.3

  • MATLAB with Simulink software R2019a

Hardware

​Architecture: 7 series and UltraScale™ FPGAs

▪ Demo board: Kintex®-7 FPGA KC705 board or Kintex UltraScale™ FPGA KCU105 board and Zynq®-7000 SoC ZC702 or ZedBoard*

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Use Simulink to perform system-level DSP design

  • Approach the complexities of high-performance DSP design

  • Describe the System Generator design flow for implementing DSP functions

  • Identify Xilinx FPGA capabilities and implement a design from algorithm concept to hardware simulation

  • List various low-level and high-level functional blocks available in System Generator

  • Run hardware co-simulation

  • Identify the high-level blocks available for FIR and FFT designs

  • Implement multi-rate systems in System Generator

  • Integrate System Generator models into the Vivado IDE

  • Design a processor-controllable interface using System Generator for DSP

  • Generate IPs from C-based design sources for use in the System Generator environment

Course Outline

Day 1:SIMULINK for Signal Processing

What is Simulink? 
Objective: Get an introduction to Simulink 

  • What is Simulink?

  • Benefits of using Simulink

  • Simulink add-ons 

  • A look at a Smulink model 

 

Creating and Simulating a Model 
Objective: Explorer the Simulink interface and block libraries. Build a simple model and analyze the simulation results. 

  • Creating and editing a Simulink model 

  • Defining system inputs and outputs

  • Simulating the model and analyzing results 

 

Modeling Discrete Dynamic System 
Objective: Model discrete dynamic systems, and visualize frame-based signals and multichannel signals using a scope. 

  • Modeling a discrete system with basic blocks

  • Finding sample times of block outputs

  • Using frames in your model

  • Using buffers 

  • Frames vs multichannel signals

  • Viewing frame-based signals

  • Behavior of delay bloacks with frame-based signals

  • Multichannel frame-based signal

 

Spectral Analysis
Objective: Perform spectral analysis in the Simulink environment, and use spectrum computation in an algorithm. 

  • Performing spectral analysis with the Spectrum Scope block

  • Choosing spectral analysis parameters

  • Analyzing power spectrum of a motor noise

  • Building a spectral classifier of speech 

  • Determining the frequency response of discrete system

DSP Design using System Generator

Day 2

  • Introduction to System Generator

  • Simulink Software Basics

  • Lab 1: Using the Simulink Software

  • Basic Xilinx Design Capture

  • Demo: System Generator Gateway Blocks

  • Lab 2: Getting Started with Xilinx System Generator

  • Signal Routing

  • Lab 3: Signal Routing

  • Implementing System Control

  • Lab 4: Implementing System Control

Day 3

Multi-Rate Systems

Lab 5: Designing a MAC-Based FIR

Filter Design

Lab 6: Designing a FIR Filter Using the FIR Compiler Block

System Generator, Vivado Design Suite, and Vivado HLS Integration

Lab 7: System Generator and Vivado IDE Integration

Kintex-7 FPGA DSP Platforms

Lab 8: System Generator and Vivado HLS Tool Integration

Lab 9: AXI4-Lite Interface Synthesis

Introduction to Model Composer

Demo: Introduction to Model Composer

[OPTIONAL]: Importing C/C++ Code to Model Composer

[OPTIONAL]: Automatic Code Generation Using Model Composer

[OPTIONAL]: Lab 10: Model Composer and Vivado IDE Integration

Lab Descriptions

  • Lab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.

  • Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.

  • Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.

  • Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.

  • Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.

  • Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.

  • Lab 7: System Generator and Vivado IDE Integration – Embed System Generator models into the Vivado IDE.

  • Lab 8: System Generator and Vivado HLS Tool Integration – Generate IP from a C-based design to use with System Generator.

  • Lab 9: AXI4-Lite Interface Synthesis – Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq SoC processor system.

  • Lab 10: Model Composer and Vivado IDE Integration - Embed a Model Composer model into the Vivado IDE.

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