FPGA Design Expert
This course is specially designed for designers new to FPGAs design or programmable logic. Build an effective FPGA design using scnchronous design techniques, instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing constraints, and use the Vivado® Design Suite to build, synthesize, implement, and download a design.
Hands-on Project on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor.
Who Should Attend
Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado® Design Suite.
TechSource Systems is the
Sole Distributor and Authorised Training Partner of Mathworks Products
Vivado Design or System Edition
Basic knowledge of the VHDL or Verilog language
Digital design knowledge
After completing this comprehensive training, you will have the necessary skills to:
Use the New Project Wizard to create a new Vivado IDE project
Describe the supported design flows of the Vivado IDE
Generate a DRC report to detect and fix design issues early in the flow
Use the Vivado IDE I/O Planning layout to perform pin assignments
Synthesize and implement the HDL design
Apply clock and I/O timing constraints and perform timing analysis
Describe the "baselining" process to gain timing closure on a design
Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
Use the Vivado logic analyzer and debug cores to debug a design
1.1 Introduction to FPGA Architecture, 3D IC, SoC
Overview of FPGA architecture, SSI technology, and SoC device architecture.
1.2 UltraFast Design Methodology: Board and Device Planning
Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.
1.3 HDL Coding Techniques
Covers basic digital coding guidelines used in an FPGA design.
1.4 Introduction to Vivado Design Flows
Introduces the Vivado design flows: the project flow and non-project batch flow.
1.5 Vivado Design Suite Project Mode
Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
1.6 Behavioral Simulation
Performs behavioral simulation for your design.
1.7 Synthesis and Implementation
Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.
1.8 Basic Design Analysis in the Vivado IDE
Use the various design analysis features in the Vivado Design Suite.
1.9 Vivado Design Rule Checks
Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations.
1.10 Vivado Design Suite I/O Pin Planning
Use the I/O Pin Planning layout to perform pin assignments in a design.
1.11 Vivado IP Flow
Customize IP, instantiate IP, and verify the hierarchy of your design IP.
2.1 Introduction to Clock Constraints
Apply clock constraints and perform timing analysis.
2.2 Generated Clocks
Use the report clock networks report to determine if there are any generated clocks in a design.
2.3 I/O Constraints and Virtual Clocks
Apply I/O constraints and perform timing analysis.
2.4 Timing Constraints Wizard
Use the Timing Constraints Wizard to apply missing timing constraints in a design.
2.5 Introduction to Vivado Reports
Generate and use Vivado timing reports to analyze failed timing paths.
2.6 Setup and Hold Timing Analysis
Understand setup and hold timing analysis.
2.7 Xilinx Power Estimator Spreadsheet
Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
2.8 Introduction to FPGA Configuration
Describes how FPGAs can be configured.
2.9 Introduction to the Vivado Logic Analyzer
Overview of the Vivado logic analyzer for debugging a design.
2.10 Introduction to Triggering
Introduces the trigger capabilities of the Vivado logic analyzer.
2.11 Debug Cores
Understand how the debug hub core is used to connect debug cores in a design.
2.12 Introduction to the Tcl Environment
Introduces Tcl (tool command language).
2.13 Using Tcl Commands in the Vivado Design Suite Project Flow
Explains what Tcl commands are executed in a Vivado Design Suite project flow.
2.14 Tcl Syntax and Structure
Understand the Tcl syntax and structure.
FPGA Design Flow Hands-on Practises