MATLAB for FPGA, ASIC, and SoC Development

Automate your workflow — from algorithm development to hardware design

and verification

Domain experts and hardware engineers use MATLAB® and Simulink® to develop prototype and production applications for deployment on FPGA, ASIC, and SoC devices.

  • Use Simulink to model and simulate digital, analog, and software together at a high level of abstraction

  • Convert to fixed-point using automated guidance, or generate native floating-point operations for any target device

  • Analyze hardware and software architectures by modeling memories, buses, and I/Os.

  • Generate optimized, readable, and traceable VHDL® or Verilog® for implementation in digital logic.

  • Generate processor-optimized C/C++ code to target embedded processors

  • Verify your algorithm running in an HDL simulator or on an FPGA or SoC device connected to your MATLAB or Simulink test bench

MATLAB and Simulink products can be used for applications such as AC motor control, software-defined radio, and embedded vision.

Use MATLAB for FPGA, ASIC, and SoC Development

Deploying LTE Wireless Communications on FPGAs: A Complete MATLAB and Simulink Workflow

Using MATLAB with Xilinx FPGAs and Zynq SoCs 

Modeling for FPGA and SoC Programming

Add hardware architecture to your algorithm using MATLAB and Simulink. This includes fixed-point quantization (30:34), you can use resources more efficiently, and native floating-point (8:55) code generation, so you can more easily program FPGAs. Reuse your tests and golden reference algorithm to simulate each successive refinement.

HDL Coder™ generates synthesizable VHDL or Verilog directly from HDL-ready Simulink and MATLAB function blocks for applications such as signal processing, wireless communications, motor and power control, and image/video processing. Xilinx System Generator for DSP and Xilinx Model Composer add Xilinx-specific blocks to Simulink for system-level simulation and hardware deployment. System Generator blocks can be integrated with native Simulink blocks for HDL code generation.

Analyze the effects of hardware and software architectures, including the use of memory and scheduling/OS effects, using SoC Blockset™.

Programming Xilinx FPGAs and Zynq SoCs

HDL Coder guides you through the steps to program your FPGA or SoC directly from Simulink without having to write a single line of code. From HDL Coder, you can optimize and generate synthesizable VHDL or Verilog along with AXI interfaces to plug into an SoC. From there you can call Embedded Coder® to generate C/C++ to program the software that runs on the embedded processor.

You can download support packages for Xilinx FPGA and Zynq SoC devices for use with Embedded Coder and HDL Coder. These automate Xilinx Vivado synthesis, place and route, and FPGA/SoC programming. Fully automated workflows are available for supported boards, and address applications such as motor control, video/image processing, and software-defined radio.

FPGA Simulation and Debugging

HDL Verifier™ reuses your MATLAB and Simulink test environments to verify your FPGA design. 

With cosimulation (5:35), you can automatically run your MATLAB or Simulink test bench connected to your Verilog or VHDL design running in a simulator from Mentor Graphics or Cadence Design Systems.

FPGA-in-the-loop simulation connects your MATLAB or Simulink test bench to supported Xilinx FPGA boards via Ethernet, JTAG, or PCI-Express (2:52).

Use MATLAB as an AXI Master interface (5:40) to send data to your FPGA, and insert data capture (4:09) logic to debug your FPGA using internal test points.

Production FPGA and SoC Design

Domain experts and hardware engineers use MATLAB and Simulink to collaborate on production FPGA and SoC design for wireless, image/video processing (20:59), motor and power control (24:20), and safety-critical applications.

HDL Coder high-level synthesis optimizations (49:42) help you meet your design’s goals while maintaining traceability between the generated RTL, the model, and the requirements, which is important for high-integrity workflows such as DO-254. Along with synthesizable VHDL and Verilog, HDL Coder generates IP cores that easily plug into Quartus Prime for system integration. And HDL Verifier generates verification models (5:19) that help speed test bench development.

Have Questions About Using MATLAB and Simulink for Predictive Maintenance

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