Xilinx

Embedded Systems

Embedded System Design

Course Description

Learn general embedded concepts, tools, and techniques using the Vivado Design Suite. The emphasis is on:

  • Designing, expanding, and modifying embedded systems utilizing the features and capabilities of the Zynq® System on a Chip (SoC), Zynq UltraScale+™ MPSoC, or MicroBlaze™ soft processor

  • Adding and simulating AXI-based peripherals using bus functional model (BFM) simulation

Partners 

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Upcoming Program

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TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products

Level

Embedded Hardware 3 

Duration

2 Days

Who Should Attend

Engineers who are interested in developing embedded systems with the Xilinx Zynq SoC, Zynq UltraScale+ MPSoC, and/or MicroBlaze soft processor core

Course Prerequisites

  • FPGA design experience

  • Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx Vivado ® software implementation tools

  • Basic understanding of C programming

  • Basic understanding of microprocessors

  • Some HDL modeling experience

Software Tools

  • Vivado Design or System Edition 2020.1

  • Vitis unified software platform 2020.1

Hardware

  • Architectures: Zynq-7000 SoC (Cortex-A9 processor), Zynq UltraScale+ MPSoC (Cortex-A53 and Cortex-R5 processors), and MicroBlaze processor

  • Demo board: Zynq UltraScale+ MPSoC ZCU104 board*

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the various tools that encompass a Xilinx embedded design

  • Rapidly architect an embedded system containing a Cortex-A9/A53/R5 or MicroBlaze processor using the Vivado IP integrator and Customization Wizard

  • Develop software applications utilizing the Vitis unified software platform

  • Create and integrate an IP-based processing system component in the Vivado Design Suite

  • Design and add a custom AXI interface-based peripheral to the embedded processing system

  • Simulate a custom AXI interface-based peripheral using verification IP (VIP)

Course Outline

Day 1

  • Embedded UltraFastDesign Methodology Outlines the different elements that comprise the Embedded Design Methodology.

  • Overview of Embedded Hardware Development Overview of the embedded hardware development flow.

  • Driving the IP Integrator Tool Describes how to access and effectively use the IPI tool.

  • Overview of Embedded Software Development Reviews the process of building a user application. Driving the Vitis Software Development Tool Introduces the basic behaviors required to drive the Vitis tool to generate a debuggable C/C++ application.

  • AXI: Introduction Introduces the AXI protocol.

  • AXI: Variations Describes the differences and similarities among the three primary AXI variations.

  • AXI: Transactions Describes different types of AXI transactions.

  • Introduction to Interrupts Introduces the concept of interrupts, basic terminology, and generic implementation.

  • Interrupts: Hardware Architecture and Support Reviews the hardware that is typically available to help implement and manage interrupts​

Day 2

  • AXI: Connecting AXI IP Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.

  • Creating a New AXI IP with the Wizard Explains how to use the Create and Import Wizard to create and package an AXI IP.

  • AXI: BFM Simulation Using Verification IP Describes how to perform BFM simulation using the Verification IP.

  • MicroBlaze Processor Architecture Overview Overview of the MicroBlaze microprocessor architecture.

  • MicroBlaze Processor Block Memory Usage Highlights how block RAM can be used with the MicroBlaze processor.

  • Zynq-7000 SoC Architecture Overview Overview of the Zynq-7000 SoC architecture.

  • Zynq UltraScale+ MPSoC Architecture Overview Overview of the Zynq UltraScale+ MPSoC architecture.​