Xilinx
Embedded Systems
Embedded System Design
Course Description
Learn general embedded concepts, tools, and techniques using the Vivado Design Suite. The emphasis is on:
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Designing, expanding, and modifying embedded systems utilizing the features and capabilities of the Zynq® System on a Chip (SoC), Zynq UltraScale+™ MPSoC, or MicroBlaze™ soft processor
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Adding and simulating AXI-based peripherals using bus functional model (BFM) simulation
Partners

Upcoming Program

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products
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Please keep me posted on the next schedule
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Please contact me to arrange customized/ in-house training
Level
Embedded Hardware 3
Duration
2 Days
Who Should Attend
Engineers who are interested in developing embedded systems with the Xilinx Zynq SoC, Zynq UltraScale+ MPSoC, and/or MicroBlaze soft processor core
Course Prerequisites
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FPGA design experience
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Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx Vivado ® software implementation tools
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Basic understanding of C programming
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Basic understanding of microprocessors
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Some HDL modeling experience
Software Tools
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Vivado Design or System Edition 2020.1
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Vitis unified software platform 2020.1
Hardware
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Architectures: Zynq-7000 SoC (Cortex-A9 processor), Zynq UltraScale+ MPSoC (Cortex-A53 and Cortex-R5 processors), and MicroBlaze processor
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Demo board: Zynq UltraScale+ MPSoC ZCU104 board*
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
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Describe the various tools that encompass a Xilinx embedded design
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Rapidly architect an embedded system containing a Cortex-A9/A53/R5 or MicroBlaze processor using the Vivado IP integrator and Customization Wizard
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Develop software applications utilizing the Vitis unified software platform
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Create and integrate an IP-based processing system component in the Vivado Design Suite
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Design and add a custom AXI interface-based peripheral to the embedded processing system
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Simulate a custom AXI interface-based peripheral using verification IP (VIP)
Course Outline
Day 1
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Embedded UltraFastDesign Methodology Outlines the different elements that comprise the Embedded Design Methodology.
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Overview of Embedded Hardware Development Overview of the embedded hardware development flow.
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Driving the IP Integrator Tool Describes how to access and effectively use the IPI tool.
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Overview of Embedded Software Development Reviews the process of building a user application. Driving the Vitis Software Development Tool Introduces the basic behaviors required to drive the Vitis tool to generate a debuggable C/C++ application.
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AXI: Introduction Introduces the AXI protocol.
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AXI: Variations Describes the differences and similarities among the three primary AXI variations.
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AXI: Transactions Describes different types of AXI transactions.
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Introduction to Interrupts Introduces the concept of interrupts, basic terminology, and generic implementation.
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Interrupts: Hardware Architecture and Support Reviews the hardware that is typically available to help implement and manage interrupts
Day 2
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AXI: Connecting AXI IP Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.
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Creating a New AXI IP with the Wizard Explains how to use the Create and Import Wizard to create and package an AXI IP.
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AXI: BFM Simulation Using Verification IP Describes how to perform BFM simulation using the Verification IP.
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MicroBlaze Processor Architecture Overview Overview of the MicroBlaze microprocessor architecture.
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MicroBlaze Processor Block Memory Usage Highlights how block RAM can be used with the MicroBlaze processor.
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Zynq-7000 SoC Architecture Overview Overview of the Zynq-7000 SoC architecture.
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Zynq UltraScale+ MPSoC Architecture Overview Overview of the Zynq UltraScale+ MPSoC architecture.