High Level Synthesis SDSoC-SDAccel
Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment
Learn how to develop, debug, and profile new or existing OpenCLTM, C/C++, and RTL applications in the SDAccelTM development environment for use on Xilinx FPGAs. Also learn how to run designs on the AlveoTM accelerator card using Nimbix Cloud.
The focus is on learning how to utilize techniques in the SDAccel environment to:
Utilize the massive parallelism inherent to FPGAs
Pipeline for performance
This course also provides an introduction to targeting the Alveo accelerator card.
Who Should Attend
Anyone who needs to accelerate their software applications using FPGAs
Understanding of Zynq®-7000 architecture (with emphasis on ACP, HP ports, and internal routing)
Comfort with the C programming language
Familiarity with the Vivado® Design Suite, Vivado HLS tool, and Xilinx SDK
SDx™ development environment 2018.3.op
Architecture: Xilinx Kintex® UltraScaleTM FPGA
After completing this training, you will know how to:
Identify candidate functions for hardware acceleration by using the TCF profiling tool
Use the System Debugger's capabilities to control the execution flow and examine memory and variables during a debug session
Move designated software functions to hardware and estimate the performance of the accelerator and the effect on the entire system
Override tool defaults to improve the performance of the individual accelerators and the overall system
Day 1 - 2
1.1 Zynq AP SoC Architecture Support for Accelerators [Optional]
Discusses the relevant aspects of the Zynq All Programmable SoC architecture for accelerator design. The focus is on AXI ports and protocols, system latency, and memory utilization.
1.2 Software Overview [Optional]
Provides a thorough understanding of how the integrated design environment works, including how the compiler and linker behave, basics of makefiles, DMA usage, and variable scope.
1.3 SDSoC Tool Overview
Introduces the purpose, underlying structures, and basic functionality of the SDSoC development environment through a combination of lecture and demonstration. Student will cement their knowledge with a lab that reinforces the concepts provided in the lecture and demo.
1.4 SDSoC Tool Design Best Practices
Illustrates common mistakes and how to avoid them. Also describes approaches to refactoring software for hardware acceleration.
1.5 Application Profiling
Profiling is the process that identifies how the processor is spending its time. Through profiling, the user can quickly identify which functions must be optimized or moved to hardware to satisfy the performance requirements.
1.6 Application Debugging
Through the use of the System Debugger, students will learn how to follow the control flow in an executing application and see the effects of the code on memory to successfully debug software issues.
1.7 Understanding Estimations in the SDSoC Tool
Once a function is moved to hardware, questions remain: Will the accelerator fit in hardware? Will it fun fast enough? Estimations can provide the answers.
1.8 Blocking vs. Non-Blocking Implementations in the SDSoC Tool
Addresses how the processor behaves while the accelerator is producing solutions—does it wait or continue on?
1.9 Implementing Multiple Accelerators in the SDSoC Tool
There are times when moving a single function to hardware is not enough—multiple functions must be moved to hardware, or one accelerator must be duplicated. Here students will learn to control how the tool produces the accelerators.
1.10 SDSoC Tool Platform Creation
Describes how to create a custom SDSoC platform starting from a hardware system built using the Vivado Design Suite, and a software run-time environment, including operating system kernel, boot loaders, file system, and libraries.
1.12 Hardware/Software Event Tracing
Hardware/software event trace helps the user to understand the performance of their application given the workload, hardware/software partitioning, and system design choices. Such information helps the user to optimize and improve system implementation.