Connectivity Design 

Designing with Multi-Gigabit Serial I/O (7 Series)

Course Description

Learn how to employ serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the 7 Series FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.


Connectivity 3 


3 days


Who Should Attend

FPGA designers and logic designers

Course Prerequisite

  • Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course

  • Familiarity with logic design (state machines and synchronous design) 

  • Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful 

  • Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

Software Tools

  • Vivado® System Edition 2015.1 

  • Mentor Graphics QuestaSim simulator 10.3d


  • Architecture: 7 series FPGAs*

  • Demo board: Kintex®-7 FPGA KC705 board*

Skills Gained

After completing this training, you will know how to:

  • Describe and utilize the ports and attributes of the serial transceiver in 7 series FPGAs 

  • Effectively utilize the following features of the gigabit transceivers:

  • 8B/10B and other encoding/decoding, comma detection, clock correction, and channel bonding

  • Pre-emphasis and linear equalization

  • Use the 7 Series FPGAs Transceivers Wizard to instantiate GT primitives in a design

  • Access appropriate reference material for board design issues involving the power supply, reference clocking, and trace design

Course Outline

Day 1

1.1 7 Series FPGAs Overview


1.2 7 Series FPGAs Transceivers Overview


1.3 7 Series FPGAs Transceivers Clocking and Resets


1.4 8B/10B Encoder and Decoder


1.5 Lab 1: 8B/10B Encoding and Bypass

Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.


1.6 Commas and Deserializer Alignment


1.7 Lab 2: Commas and Data Alignment

Use programmable comma detection to align a serial data stream.

Day 2

2.1 RX Elastic Buffer and Clock Correction


2.2 Lab 3: Clock Correction

Utilize the attributes and ports associated with clock correction to compensate for frequency differences on the TX and RX clocks.


2.3 Channel Bonding


2.4 Lab 4: Channel Bonding

Modify a design to use two transceivers bonded together to form one virtual channel.


2.5 Transceiver Wizard Overview

2.6 Lab 5: Transceiver Core Generation

Use the 7 Series FPGAs Transceivers Wizard to create instantiation templates.


2.7 Lab 6: Simulation

Simulate the transceiver IP using the IP example design.


2.8 Transceiver Implementation


2.9 Lab 7: Implementation

Implement the transceiver IP using the IP example design.


2.10 Physical Media Attachments

Day 3

3.1 64B/66B Encoding and the Gearbox

Implement the transceiver IP using the IP example design.


3.2 Lab 8: 64B/66B Encoding

Generate a 64B/66B core by using the 7 Series FPGAs Transceivers Wizard, simulate the design, and analyze the results.


3.3 Transceiver Board Design Considerations


3.4 Transceiver Test and Debugging


3.5 Lab 9: Transceiver Debugging

Debug the transceiver IP using the IP example design and Vivado debug cores.


3.6.1 Lab 10: IBERT Lab

Create an IBERT design to verify physical links. (Choose Lab 10 or 11.)


3.6.2 Lab 11: System Lab

Perform all design steps from planning the design, generating the core, integrating the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board. (Choose Lab 10 or 11.)


3.7 Transceiver Application Examples



Upcoming Program

xilinx ATP 黑.png

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products