Xilinx
Languages
Designing with Verilog
Course Description
This course provides a thorough introduction to the Verilog language. The emphasis is on:
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Writing efficient hardware designs
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Performing high-level HDL simulations
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Employing structural, register transfer level (RTL), and behavioral coding styles
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Targeting Xilinx devices specifically and FPGA devices in general
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Utilizing best coding practices
This course covers Verilog 1995 and 2001.
Partners

Upcoming Program

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products
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Please keep me posted on the next schedule
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Please contact me to arrange customized/ in-house training
Duration
3 Days
Who Should Attend
Level
FPGA 1
Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs
Prerequisites
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Basic digital design knowledge
Software Tools
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Vivado® Design Suite 2020.1
Hardware
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Architecture: N/A*
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Demo board: Zynq® UltraScale+™ MPSoC ZCU104 board*
Skills Gained
After completing this comprehensive training, you will have the necessary skills for:
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Write RTL Verilog code for synthesis
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Write Verilog test fixtures for simulation
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Create a Finite State Machine (FSM) by using Verilog
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Target and optimize Xilinx FPGAs by using Verilog
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Use enhanced Verilog file I/O capability
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Run a timing simulation by using Xilinx Simprim libraries
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Create and manage designs within the Vivado Design Suite environment
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Download to the evaluation demo board
Course Outline
Day 1
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Introduction to Verilog Discusses the history of the Verilog language and provides an overview of the different features of Verilog.
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Verilog Keywords and Identifiers Discusses the data objects that are available in the Verilog language as well as keywords and identifiers.
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Verilog Data Values and Number Representation Covers what data values are in Verilog, as well as how to represent numbers in Verilog.
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Verilog Data Types Covers the various data types in Verilog.
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Verilog Buses and Arrays Covers buses and arrays in Verilog.
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Verilog Modules and Ports Describes both the syntax and hierarchy for a Verilog module, port declarations, and the difference between reg versus wire.
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Verilog Operators Shows the syntax for all Verilog operators.
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Continuous Assignment Introduces the Verilog continuous assignment statement.
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Gate-Level Modeling Introduces gate-level modeling in Verilog
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Procedural Assignment Provides an introduction to procedural assignments in Verilog, including their usage and restrictions.
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Blocking and Non-Blocking Procedural Assignment Introduces blocking and non-blocking assignment statements in Verilog.
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Procedural Timing Control Introduces the timing control methods that are used in procedural assignments.
Day 2
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Verilog Conditional Statements: if_else Describes the if/else conditional statement.
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Verilog Conditional Statements: case Describes the case conditional statement.
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Verilog Loop Statements Introduces the different types of Verilog loop statements.
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Introduction to the Verilog Testbench Introduces the concept of the Verilog testbench.
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System Tasks Provides a basic understanding of system tasks.
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Verilog Subprograms Covers the use of subprograms in verification and RTL code to model functional blocks.
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Verilog Function Describes s functions, which are integral to reusable and maintainable code.
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Verilog Tasks Covers tasks in Verilog.
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Verilog Compiler Directives Describes Verilog compiler directives.
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Verilog Parameters Covers Verilog parameters and the local parameter concept.
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Verilog Generate Statement Introduces the Verilog generate statement.
Day 3
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Verilog Timing Checks Covers the timing check statements in Verilog and talks about the specify block.
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Finite State Machines Provides an overview of finite state machines, one of the more commonly used circuits.
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Mealy Finite State Machine Describes the Mealy FSM and how to code for it.
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Moore Finite State Machine Describes the Moore FSM and how to code for it.
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FSM Coding Guidelines Shows how to model an FSM of any complexity in Verilog and describes recommendations for performance and reliability.
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Avoiding Race Conditions in Verilog Describe what a race condition is and provides steps to avoid this condition.
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File I/O: Introduction Covers using basic and enhanced Verilog file I/O capabilities for more robust design verification.
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File I/O: Read Functions Covers Verilog file I/O read capabilities.
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File I/O: Write Functions Covers Verilog file I/O write capabilities.
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Targeting Xilinx FPGAs Focuses on Xilinx-specific implementation and chip-level optimization.
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User-Defined Primitives Describes user-defined primitives (UDPs).
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Programming Language Interface Introduces the programming language interface(PLI) in Verilog.