Xilinx
Connectivity Design
Designing with Xilinx Serial Transceivers
Learn how to employ serial transceivers in UltraScale and UltraScale+ FPGA designs or Zynq UltraScale+ MPSoC designs.
The focus is on:
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Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection
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Utilizing the Transceivers Wizards to instantiate transceiver primitives
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Synthesizing and implementing transceiver designs
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Taking into account board design as it relates to the transceivers
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Testing and debugging
Duration
2 days
Who Should Attend
FPGA designers and logic designers
Prerequisites
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Verilog experience (or the Designing with Verilog or the Designing with VHDL course)
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Familiarity with logic design (state machines and synchronous design)
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Basic knowledge of FPGA architecture and Xilinx implementation tools are helpful
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Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Software Tools
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Vivado® System Edition 2019.1
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Mentor Graphics Questa Advanced Simulator 10.7
Hardware
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Architecture: all UltraScale Architectures
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Demo board: Kintex® UltraScale FPGA KCU105 board or Zynq UltraScale+ MPSoC ZCU104 board
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
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Describe and use the ports and attributes of the serial transceivers in Xilinx FPGAs and MPSoCs
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Effectively use the following features of the gigabit transceivers:
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64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
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Pre-emphasis and receive equalization
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Use the Transceivers Wizards to instantiate GT primitives in a design
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Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
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Use the IBERT design to verify transceiver links on real hardware
Course Outline
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UltraScale, UltraScale+, Zynq UltraScale+ Device Transceivers Overview
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UltraScale, UltraScale+, Zynq UltraScale+ Device Transceivers Clocking and Resets
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Transceiver IP Generation – Transceiver Wizard
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Lab 1: Transceiver Core Generation
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Transceiver Simulation
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Lab 2: Transceiver Simulation
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PCS Layer General Functionality
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PCS Layer Encoding
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Lab 3: 64B/66B Encoding
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Transceiver Implementation
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Lab 4: Transceiver Implementation
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PMA Layer Details
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PMA Layer Optimization
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Lab 5: IBERT Design
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Transceiver Test and Debugging
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Lab 6: Transceiver Debugging
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Transceiver Board Design Considerations
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Transceiver Application Examples
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Optional: Additional modules on Virtex® UltraScale+ FPGA GTM transceiver architecture and functionality
Lab Descriptions
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Lab 1: Transceiver Core Generation – Use the Transceivers Wizard to create instantiation templates.
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Lab 2: Transceiver Simulation – Simulate the transceiver IP by using the IP example design.
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Lab 3: 64B/66B Encoding – Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.
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Lab 4: Transceiver Implementation – Implement the transceiver IP by using the IP example design.
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Lab 5: IBERT Design – Verify transceiver links on real hardware.
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Lab 6: Transceiver Debugging – Debug transceiver links.
Partners

TechSource Systems is the
Sole Distributor and Authorised Training Partner of Mathworks Products
Upcoming Program
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Please keep me posted on the next schedule
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Please contact me to arrange customized/ in-house training