Xilinx

Connectivity Design 

Designing an Integrated PCI Express System

Course Description

Attending this course will provide students a working knowledge of how to implement a Xilinx PCI Express® core in custom applications. This course offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This course focuses on the AXI streaming interconnect.

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Level

Connectivity 3 

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Duration

2 days

 

Who Should Attend

  • Hardware designers who want to create applications using Xilinx IP cores for PCI Express 

  • Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution

  • System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications  

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Course Prerequisite

  • Experience with PCIe specification protocol

  • Knowledge of VHDL or Verilog

  • Some experience with Xilinx implementation tools

  • Some experience with a simulation tool, preferably the Vivado® simulator

  • Moderate digital design experience

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Software Tools

  • Vivado Design or System Edition 2017.1

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Hardware

  • Architecture: UltraScale™ and 7 series FPGAs*

  • Demo board: Kintex® UltraScale FPGA KCU105 board or Kintex-7 FPGA KC705 board*

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Skills Gained

After completing this training, you will know how to:

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  • Construct a basic PCIe system by:

    • Selecting the appropriate core for your application

    • Specifying requirements of an endpoint application

    • Connecting this endpoint with the core

    • Utilizing FPGA resources to support the core

    • Simulating the design

  • Identify the advanced capabilities of the PCIe specification protocol and feature set 

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Course Outline

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Day 1

1.1  Course Introduction

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1.2  Lab 0: Packet Coding

This lab helps you recall basic PCI Express transaction layer packet formats.

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1.3  Xilinx PCI Express Solutions

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1.4  Connecting Logic to the Core – AXI Interface

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1.5  PCIe Core Customization

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1.6  Lab 1: Constructing the PCIe Core

This lab familiarizes you with the necessary flow for generating a Xilinx integrated PCI Express Endpoint core from the IP catolog. You will select appropriate parameters and create the PCIe core used throughout the labs.

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1.7  Packet Formatting Details

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1.8  Simulating a PCIe System Design

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1.9  Lab 2: Simulating the PCIe Core

This lab demonstrates the timing and behaviour of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets.

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1.10  Endpoint Application Considerations

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1.11  PCI Express in Embedded Systems

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Day 2

2.1  Lab 3: Using the PCI Express Core in IP Integrator

This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design.

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2.2  Application Focus: DMA

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2.3  Design Implementation and PCIe Configuration

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2.4  Lab 4: Implementing the PCIe Design

This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode.

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2.5  Root Port Applications

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2.6  Debugging and Compliance

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2.7  Lab 5: Debugging the PCIe Design

This lab illustrates how to use the Vivado logic analyser to monitor the behaviour of the core and a small endpoint application for proper operation.

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2.8  Interrupts and Error Management

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2.9  Course Summary

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