Designing FPGAs Using the Vivado Design Suite 4 - Advanced
This course tackles the most sophisticated aspects of the Vivado® Design Suite and Xilinx hardware. This course enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.
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Who Should Attend
Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity
Vivado System Edition 2016.3
Architecture: UltraScale™ and 7 series FPGAs*
Demo board: Kintex®-7 FPGA KC705 board*
After completing this comprehensive training, you will have the necessary skills to:
Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
Analyze a timing report to identify how to center the clock in the data eye
Use Tcl scripting in non-project batch flows to synthesize, implement, and generate custom timing reports
Utilize floorplanning techniques to improve design performance
Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
Utilize Xilinx security features, bitstream encryption, and authentication using AES for design and IP security
Identify advanced FPGA configurations, such as daisy chains and gangs, for configuring multiple FPGAs in a design
Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset
1.1 UltraFast Design Methodology Introduction
Introduces the UltraFast™ methodology guidelines covered in this course.
1.2 Scripting in Vivado Design Suite Non-Project Mode
Write Tcl commands in the non-project batch flow for a design.
1.3 Using Procedures and Lists in Tcl Scripting
Employ procedures and lists in Tcl scripting.
1.4 Using regexp in Tcl Scripting
Use regular expressions to find a pattern in a text file while scripting an action in the Vivado Design Suite.
1.5 Introduction to the Xilinx Tcl Store
Introduces the Xilinx Tcl Store.
1.6 Debugging and Error Management in Tcl Scripting
Understand how to debug errors in a Tcl script.
1.7 I/O Timing Scenarios
Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data.
1.8 Source-Synchronous I/O Timing
Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.
1.9 System-Synchronous I/O Timing
Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface.
1.10 Timing Constraints Priority
Identify the priority of timing constraints.
1.11 Case Analysis
Understand how to analyze timing when using multiplexed clocks in a design.
1.12 Daisy Chains and Gangs in Configuration
Introduces advanced configuration schemes for multiple FPGAs.
1.13 Managing Remote IP
Store IP and related files remote to the current working project directory.
2.1 Introduction to Floorplanning
Introduction to floorplanning and how to use Pblocks while floorplanning.
2.2 Design Analysis and Floorplanning
Explore the pre- and post-implementation design analysis features of the Vivado IDE.
2.3 Incremental Compile Flow
Utilize the incremental compile flow when making last-minute RTL changes.
2.4 Physical Optimization
Use physical optimization techniques for timing closure.
2.5 Vivado Design Suite ECO Flow
Use ECO flow to make changes to a previously implemented design and apply changes to the original design.
2.6 Trigger and Debug at Device Startup
Debug the events around the device startup.
2.7 Scripting for a VLA Design
Use Tcl scripting for VLA designs for adding probes and making connections to probes.
2.8 Vivado Design Suite Debug Methodology
Employ the debug methodology for debugging a design using the Vivado logic analyzer.
2.9 Power Management Techniques
Identify techniques used for low power design.
2.10 Bitstream Security
Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and