Xilinx
FPGA Design
Designing FPGAs Using the Vivado Design Suite 4 - Advanced
Course Description
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Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware. The focus is on:
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Applying timing constraints for source-synchronous and system-synchronous interfaces
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Utilizing floorplanning techniques
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Employing advanced implementation options
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Utilizing Xilinx security features
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Identifying advanced FPGA configurations
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Debugging a design at the device startup phase
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This is the final course in the Designing FPGAs Using the Vivado
Partners

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products
Upcoming Program
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Please keep me posted on the next schedule
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Please contact me to arrange customized/ in-house training

Who Should Attend
Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity
Duration
2 Days
Level
FPGA 4
Course Prerequisites
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At least six months of design experience with Xilinx tools and FPGAs
Software Tools
Vivado Design or System Edition 2020.1
Hardware
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Architecture: UltraScale™ family*
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Demo board: Zynq® UltraScale+™ ZCU104 board
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
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Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
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Analyze a timing report to identify how to center the clock in the data eye
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Utilize floorplanning techniques to improve design performance
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Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
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Utilize Xilinx security features, bitstream encryption, and authentication using AES for design and IP security
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Identify advanced FPGA configurations, such as daisy chains and gangs, for configuring multiple FPGAs in a design
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Debug a design at the device startup phase to debug issues related to startup events, suchas MMCM lock and design coming out of reset
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Use Tcl scripting in non-project batch flows to synthesize, implement, and generate custom timing reports
Course Outline
Day 1
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UltraFast Design Methodology: Design Closure Introduces the UltraFast™ design methodology guidelines covered in this course.
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Scripting in Vivado Design Suite Non-Project Mode Write Tcl commands in the non-project batch flow for a design.
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Hierarchical Design Overview of the hierarchical design flows in the Vivado Design Suite.
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Managing Remote IP Store IP and related files remote to the current working project directory.
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I/O Timing Scenarios Overview of various I/O timing scenarios, such as source-and system-synchronous, direct/MMCM capture, and edge/center aligned data.
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System-Synchronous I/O Timing Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface.
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Source-Synchronous I/O Timing Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.
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Timing Constraints Priority Identify the priority of timing constraints.
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Case Analysis Understand how to analyze timing when using multiplexed clocks in a design.
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Introduction to Floorplanning Introduction to floorplanning and how to use Pblocks while floorplanning.
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Design Analysis and Floorplanning Explore the pre-and post-implementation design analysis features of the Vivado IDE.
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Congestion Identifies congestion and addresses congestion issues.
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Introduction to the Xilinx XHub Stores Introduces the Xilinx XHub Stores.
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Incremental Compile Flow Utilize the incremental compile flow when making last-minute RTL changes.
Day 2
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Timing Closure Using Physical Optimization Techniques Use physical optimization techniques for timing closure.
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Vivado Design Suite ECO Flow Use the ECO flow to make changes to a previously implemented design and apply changes to the original design.
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Power Management Techniques Identify techniques used for low power design.
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Daisy Chains and Gangs in Configuration Introduces advanced configuration schemes for multiple FPGAs.
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Bitstream Security Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication.
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Vivado Design Suite Debug Methodology Understand and follow the debug core recommendations. Employ the debug methodology for debugging a design using the Vivado logic analyzer.
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Trigger and Debug at Device Startup Debug the events around the device startup.
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Trigger Using the Trigger State Machine in the Vivado Logic Analyzer Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer.
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Debugging the Design Using Tcl Commands Use Tcl scripting for VLA designs for adding probes and making connections to probes.
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Using Procedures in Tcl Scripting Employ procedures in Tcl scripting.
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Using Lists in Tcl Scripting Employ lists in Tcl scripting.
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Using Regular Expressions in Tcl Scripting Use regular expressions to find a pattern in a text file while scripting an action in the Vivado Design Suite.
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Debugging and Error Handling in Tcl Scripts Understand how to debug errors in a Tcl script.