Designing FPGAs Using the Vivado Design Suite 3
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado logic analyzer.
TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products
Who Should Attend
FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado® Design Suite
Architecture: UltraScale™ and 7 series FPGAs*
Demo board: Kintex®-7 FPGA KC705 board*
Vivado Design or System Edition 2016.3
After completing this comprehensive training, you will know how to:
Employ good alternative design practices to improve design reliability
Define a properly constrained design
Apply baseline constraints to determine if internal timing paths meet design timing objectives
Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
Increase performance by utilizing FPGA design techniques
Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
1.1 UltraFast Design Methodology Introduction
Introduces the methodology guidelines covered in this course.
1.2 Timing Simulation
Simulate the design post-implementation to verify that a design works properly on hardware.
1.3 Vivado Design Suite Non-Project Mode
Create a design in the Vivado Design Suite non-project mode.
1.4 Revision Control Systems in the Vivado Design Suite
Use version control systems with Vivado design flows.
Use Xilinx-recommended baselining procedures to progressively meet timing closure.
Use pipelining to improve design performance.
Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
1.8 Report Clock Interaction
Use the clock interaction report to identify interactions between clock domains.
2.1 Synchronization Circuits
Use synchronization circuits for clock domain crossings.
2.2 Report Datasheet
Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
2.3 Configuration Modes
Understand various configuration modes and select the suitable mode for a design.
2.4 Dynamic Power Estimation Using Vivado Report Power
Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.
2.5 Debug Flow in an IP Integrator Block Design
Insert the debug cores into IP integrator block designs.
2.6 Remote Debugging Using the Vivado Logic Analyzer
Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location.
2.7 JTAG-to-AXI-Master Core
Use this debug core to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware.
2.8 Trigger Using the Trigger State Machine in the Vivado Logic Analyzer
Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer.
2.9 Manipulating Design Properties Using Tcl
Query your design and make pin assignments by using various Tcl commands.