Xilinx

FPGA Design

Designing FPGAs Using the Vivado Design Suite 3

Course Description

Learn how to effectively employ timing closure techniques. This course includes: 

  • Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits

  • Showing optimum HDL coding techniques that help with design timing closure

  • Illustrating the advanced capabilities of the Vivado® logic analyzer to debug a design

This course builds further on the previous Designing FPGAs Using the Vivado Design Suite courses.

Partners 

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products

Upcoming Program

Who Should Attend

FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado Design Suite

Duration

2 Days

Level

FPGA 3

Course Prerequisites

Optional Videos

  • Basic HDL Coding Techniques*

  • Power Estimation*

Go to www.xilinx.com/training and click the Online Training tab to view these videos.

Software Tools

Vivado Design or System Edition 2020.1

Hardware

  • Architecture: UltraScale™ family**

  • Demo board: Zynq® UltraScale+™ ZCU104 board

Skills Gained

** This course focuses on the UltraScale architecture. After completing this comprehensive training, you will have the necessary skills to:

  • Employ good alternative design practices to improve design reliability

  • Define a properly constrained design

  • Apply baseline constraints to determine if internal timing paths meet design timing objectives

  • Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals

  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle

  • Increase performance by utilizing FPGA design techniques

  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report

  • Describe how to enable remote debug

Course Outline

Day 1

  • UltraFast Design Methodology: Implementation Introduces the methodology guidelines coveredin this course.

  • Vivado Design Suite Non-Project Mode Create a design in the Vivado Design Suite non-project mode.

  • Baselining Use Xilinx-recommended baselining procedures to progressively meet timing closure. PipeliningUse pipelining to improve design performance.

  • Inference Infer Xilinx dedicated hardware resources by writing appropriate HDL code.

  • Revision Control Systems in the Vivado Design Suite Use version control systems with Vivado design flows.

  • Timing Simulation Simulate the design post-implementation to verify that a design works properly on hardware.

  • Synchronization Circuits Use synchronization circuits for clock domain crossings.

Day 2

  • Report Clock InteractionUse the clock interaction report to identify interactions between clock domains.

  • Report Datasheet Use the datasheet report to find the optimal setup and hold margin for an I/O interface.

  • Report QoR Use the QoR Assessment and QoR Suggestions reports to analyze the timing for a design.

  • Dynamic Power Estimation Using VivadoReport Power Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.

  • Configuration Modes Understand various configuration modes and select the suitable mode for a design.

  • Netlist Insertion Debug Probing Flow Covers the netlist insertion flow of the debug using the Vivado logic analyzer.

  • Sampling and Capturing Data in Multiple Clock Domains Overview of debugging a design with multiple clock domains that require multiple ILAs.

  • JTAG to AXI Master Core Use this debug core to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware.

  • Debug Flow in an IP Integrator Block Design Insert the debug cores into IP integrator block designs. Remote Debugging Using the Vivado Logic AnalyzerUse the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location.

  • Manipulating Design Properties Using Tcl Query your design and make pin assignments by using various Tclcommands.