Xilinx

FPGA Design

Designing FPGAs Using the Vivado Design Suite 2

Course Description

Learn how to build a more effective FPGA design: The focus is on:

• Using synchronous design techniques

• Utilizing the Vivado® IP integrator to create a sub-system

• Employing proper HDL coding techniques to improve design performance

• Debugging a design with multiple clock domains This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.

Who Should Attend

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Duration

2 Days

Level

FPGA 2

Course Prerequisites

• Designing FPGAs Using the Vivado Design Suite 1 course

• Working HDL knowledge (VHDL or Verilog)

• Digital design experience

Software Tools

Vivado Design or System Edition 2020.1

Hardware

• Architecture: UltraScale™ family

• Demo board (optional): Zynq® UltraScale+™ MPSoC ZCU104 board**

Optional Video

Basic HDL Coding Techniques*Go to and click the Online Training tab to view this video

Skills Gained

• Identify synchronous design techniques

• Build resets into your system for optimum reliability and design speed

• Create a Tcl script to create a project, add sources, and implement a design

• Describe and use the clock resources in a design

• Create and package your own IP and add to the Vivado IP catalog to reuse

• Use the Vivado IP integrator to create a block design

• Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design

• Describe how power analysis and optimization is performed

• Describe the HDL instantiation flow of the Vivado logic analyzer

Course Outline

Day 1

• UltraFast Design Methodology: Design Creation Overview of the methodology guidelines covered in this course.

• Synchronous Design Techniques Introduces synchronous design techniques used in an FPGA design.

• Resets Investigates the impact of using asynchronous resets in a design.

• Register Duplication Use register duplication to reduce high fanout nets in a design.

• Scripting in Vivado Design Suite Project Mode Explains how to write Tcl commands in the project-based flow for a design.

• Clocking Resources Describes various clock resources, clocking layout, and routing in a design.

• I/O Logic Resources Overview of I/O resources and the IOB property fortiming closure.

• Creating and Packaging Custom IP Create your own IP and package and include it in the Vivado IP catalog.

Day 2

• Using an IP Container Use a core container file as a single file representation for an IP.

• Designing with the IP Integrator Use the Vivado IP integrator to create the uart_led subsystem.

• Timing Constraints Editor Introduces the timing constraints editor tool to create timing constraints.

• Report Clock Networks Use report clock networks to view the primary and generated clocks in a design.

• Timing Summary Report Use the post-implementation timing summary report to sign-off criteria for timing closure.

• Clock Group Constraints Apply clock group constraints for asynchronous clock domains. Introduction to Timing Exceptions Introduces timing exception constraints and applying them to fine tune design timing.

• Analysis and Optimization Using the Vivado Design Suite Use report power commands to estimate power consumption.

• Configuration Process Understand the FPGA configuration process, such as device power up, CRC check, etc.

• HDL Instantiation Debug Probing Flow Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.

• Design Analysis Using Tcl Commands Analyze a design using Tcl commands.