Xilinx
FPGA Design
Designing FPGAs Using the Vivado Design Suite 2
Course Description
Learn how to build a more effective FPGA design: The focus is on:
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Using synchronous design techniques
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Utilizing the Vivado® IP integrator to create a sub-system
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Employing proper HDL coding techniques to improve design performance
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Debugging a design with multiple clock domains This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.
Partners

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products
Upcoming Program
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Please keep me posted on the next schedule
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Please contact me to arrange customized/ in-house training

Who Should Attend
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
Duration
2 Days
Level
FPGA 2
Course Prerequisites
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Working HDL knowledge (VHDL or Verilog)
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Digital design experience
Software Tools
Vivado Design or System Edition 2020.1
Hardware
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Architecture: UltraScale™ family
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Demo board (optional): Zynq® UltraScale+™ MPSoC ZCU104 board**
Optional Video
Basic HDL Coding Techniques*Go to and click the Online Training tab to view this video
Skills Gained
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Identify synchronous design techniques
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Build resets into your system for optimum reliability and design speed
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Create a Tcl script to create a project, add sources, and implement a design
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Describe and use the clock resources in a design
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Create and package your own IP and add to the Vivado IP catalog to reuse
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Use the Vivado IP integrator to create a block design
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Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
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Describe how power analysis and optimization is performed
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Describe the HDL instantiation flow of the Vivado logic analyzer
Course Outline
Day 1
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UltraFast Design Methodology: Design Creation Overview of the methodology guidelines covered in this course.
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Synchronous Design Techniques Introduces synchronous design techniques used in an FPGA design.
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Resets Investigates the impact of using asynchronous resets in a design.
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Register Duplication Use register duplication to reduce high fanout nets in a design.
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Scripting in Vivado Design Suite Project Mode Explains how to write Tcl commands in the project-based flow for a design.
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Clocking Resources Describes various clock resources, clocking layout, and routing in a design.
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I/O Logic Resources Overview of I/O resources and the IOB property fortiming closure.
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Creating and Packaging Custom IP Create your own IP and package and include it in the Vivado IP catalog.
Day 2
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Using an IP Container Use a core container file as a single file representation for an IP.
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Designing with the IP Integrator Use the Vivado IP integrator to create the uart_led subsystem.
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Timing Constraints Editor Introduces the timing constraints editor tool to create timing constraints.
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Report Clock Networks Use report clock networks to view the primary and generated clocks in a design.
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Timing Summary Report Use the post-implementation timing summary report to sign-off criteria for timing closure.
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Clock Group Constraints Apply clock group constraints for asynchronous clock domains. Introduction to Timing Exceptions Introduces timing exception constraints and applying them to fine tune design timing.
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Analysis and Optimization Using the Vivado Design Suite Use report power commands to estimate power consumption.
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Configuration Process Understand the FPGA configuration process, such as device power up, CRC check, etc.
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HDL Instantiation Debug Probing Flow Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.
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Design Analysis Using Tcl Commands Analyze a design using Tcl commands.