Xilinx

FPGA Design

Designing FPGAs Using the Vivado Design Suite 1

Course Description

This course offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.

The course provides experience with:

 Creating a Vivado Design Suite project with source files

 Simulating a design

 Performing pin assignments

 Applying basic timing constraints

 Synthesizing and implementing

 Debugging a design

 Generating and downloading a bitstream onto a demo board

What's New for 2019.2

 Introduction to FPGA Architecture, 3D ICs, SoCs: Description of 20nm FPGA capabilities

 HDL Coding Techniques: Auto-pipelining considerations

 Vivado Synthesis and Implementation: Clarification on PhysOpt option enablement in the Default implementation strategy

 Basics of Static Timing Analysis and Calculating Setup and Hold Timing: Previous Setup and Hold Timing Analysis topic split into these two topics

Partners 

Upcoming Program

TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products

Who Should Attend

Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite

Duration

2 Days

Recommended Recorded Videos

  • Basic FPGA Architecture: Slice and I/O Resources*

  • Basic FPGA Architecture: Memory and Clocking Resources*

Course Prerequisites

  • Basic knowledge of the VHDL or Verilog language

  • Digital design knowledge

SoftwareTools

  • Vivado Design or System Edition 2019.2​

  • Basic FPGA Architecture: Slice and I/O Resources*

  • Basic FPGA Architecture: Memory and Clocking Resources*

Hardware

  • Architecture: UltraScale™ family**

  • Demo board: Zynq® UltraScale+™ MPSoC ZCU104 board**

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • ​Use the New Project Wizard to create a new Vivado IDE project

  • Describe the supported design flows of the Vivado IDE

  • Generate a DRC report to detect and fix design issues early in the flow

  • Use the Vivado IDE I/O Planning layout to perform pin assignments

  • Synthesize and implement the HDL design

  • Apply clock and I/O timing constraints and perform timing analysis

  • Describe the "baselining" process to gain timing closure on a design

  • Use the Schematic and Hierarchy viewers to analyze and cross-probe a design

  • Use the Vivado logic analyzer and debug cores to debug a design

Course Outline

Day 1

Introduction to FPGA Architecture, 3D ICs, SoCs

Overview of FPGA architecture, SSI technology, and SoC device architecture. {Lecture}

UltraFast Design Methodology: Board and Device Planning

Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist. {Lecture, Demo}

HDL Coding Techniques

Covers basic digital coding guidelines used in an FPGA design. {Lecture}

Introduction to Vivado Design Flows

Introduces the Vivado design flows: the project flow and non-project batch flow. {Lecture}

Vivado Design Suite Project-based Flow

Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design. {Lecture, Lab}

Behavioral Simulation

Describes the process of behavioral simulation and the simulation options available in the Vivado® IDE. {Lecture}

Vivado Synthesis and Implementation

Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board. {Lecture, Lab}

Basic Design Analysis in the Vivado IDE

Use the various design analysis features in the Vivado Design Suite. {Lab, Demo}

Vivado Design Rule Checks

Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations. {Lab}

Vivado Design Suite I/O Pin Planning

Use the I/O Pin Planning layout to perform pin assignments in a design. {Lecture, Lab}

Vivado IP Flow

Customize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Demo, Lab}

Day 2

Introduction to Clock Constraints

Apply clock constraints and perform timing analysis. {Lecture, Demo, Lab}

Generated Clocks

Use the report clock networks report to determine if there are any generated clocks in a design. {Lecture, Demo}  I/O Constraints and Virtual Clocks

Apply I/O constraints and perform timing analysis. {Lecture, Lab}

  • Facebook Social Icon
  • Twitter Social Icon
  • Google+ Social Icon
  • YouTube Social  Icon
  • Pinterest Social Icon
  • Instagram Social Icon
icons8-facebook-circled-48.png
icons8-linkedin-circled-48.png
All rights reserved. Copyright © TechSource Systems Pte Ltd.
Company Registration No. 199603163W