High Level Synthesis SDSoC-SDAccel  

Deep Learning on FPGA with SDSoC

Course Description

This course is specially designed for designers new to DeepLearning design or application. The introduction to the theoretical principle, effective comprehension of training and testing flow using Caffe Framwork, demonstrate impressive project demo, understand the design flow with C/C++ coding techniques, use little HDL coding techniques and more C coding techniques to apply Deeplearning demo on edge of FPGA device. 

Participants will be taught the necessary knowledge to Comprenhend the theoretical principle, training, testing and process about application on FPGA device.  Participants will be able to test their knowledge and apply their skills on Deeplearning immediately. You will be able to face the real challenge to do a primary Deeplearning design flow project with the guidance of our instructor. 


4 Days

Course Prerequisites

  • • Understanding of Zynq®-7000 architecture (with emphasis on ACP, HP ports, and internal routing)
    • Comfort with the C programming language/ Python
    • Familiarity with the Vivado® Design Suite, Vivado HLS tool, and Xilinx SDK

Software Tools

  • Vivado Design Suite and SDx™ development environment 2017.1 or any other latest version based on notes availability. 

Software Tools

EagleGo-HD Smart Vision Kit

Course Outline

Day 1​


1.1  Introduction to DeepLearning

Overview of DeepLearning origin and development, propose the process and methodology of Deeplearning design.

1.2   Introduction to Artifical and Convolutional Neural Network

Overview of Convolutional Neural Network and introduces the mathematical model of Artifical Neural Network.

1.3   DeepLearning Design Methodology 

Introduces the methodology guidelines covered the DeepLearning training stage and the design flow.

1.4   Introduction to the Architecture of Convolutional Neural Network

Introduces the primary network layers in the architecture of Convolution Neural Network.

1.5   Installation about Caffe framework

Introduces the process of installation about Deeplearning framework Caffe, including the setting of enviroment about caffe, python, etc.

1.6   Introduction to network structure files in Caffe

Introduces the details of network structure about the Cifar10 demo in Caffe and the basic knowledge for training and testing.

1.7   Process on training and testing with the Cifar10 demo

Demostrate the process of training and testing with Cifar10 demo, comprehend the implication of data on testing process. 

1.8   Experiments about Mnist Dataset demo

Interactions using experiments about Mnist Dataset demo with Python coding techniques.

1.9  Hands-on operation and experiment

Day 2

2.1  Review 

Review the foundations about DeepLearning on Caffe.

2.2  Introduction to Forward Propagation

Introduces the design of Forward Propagation with C coding techniques and demonstrate the Inference demo about Cifar10 demo to identify airplane, automobile, bird, horse, etc.

2.3  Introduction to Backward Propagation

Introduces the theoretical principle and derivation process about Backward Propagation.

2.4  Introduction to training and testing demo

Demonstrate the training and testing demo and introduce structures and codes about the demo with C++ coding techniques.

2.5  Hands-on operation and experiment

Day 3-4

4.1  SDSoC Tool Overview

Explain the advantages of using the SDSoC development environment and describe the typical SDSoC development flow.

4.2  Tools Collection

Introduces the Tools:sdsoc IDE involes a lot of tools ,CDT,TCF,sdscc/sds++ ...

4.3  SDSoC Platform Creation

Introduces the SDSoC Platform structure and how to create a new platform 

4.4  Understanding Estimations in the SDSoC Tool 

Introduces the Estimations tool in the SDSOC:estimations the source of FPGA when generated a new accelarator.

4.5  Pragma Syntax 

Understand the pragma syntax and Use Pragma to get better performance.

4.6  Introduction to Deeplearning demo complete with SDSOC Design Suite

Using sdsoc accelerate complex algorithm :complex algorithms are implemented in FPGA .

4.7  Hands-on operation and experiment



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