Xilinx

High Level Synthesis SDSoC-SDAccel  

C-based Design: High-Level Synthesis with the Vivado HLS Tool

Course Description

This course provides a thorough introduction to the Vivado® High-Level Synthesis (HLS) tool. The focus is on:

  • Covering synthesis strategies and features

  • Improving throughput, area, interface creation, latency, testbench coding, and coding tips

  • Utilizing the Vivado HLS tool to optimize code for high-speed performance in an embedded environment

  • Downloading for in-circuit validation Level

Level

DSP 3 

Duration

2 days

Who Should Attend

Software and hardware engineers looking to utilize high-level synthesis

Course Prerequisites

  • C, C++, or System C knowledge

  • High-level synthesis for software engineers OR high-level synthesis for hardware engineers

Software Tools

  • Vivado HLS System Edition 2020.1

  • Vitis unified software platform 2020.1

Hardware

  • Architecture: Zynq UltraScale+ MPSoC

  • Demo board: Zynq UltraScale+ MPSoC ZCU104 board*

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Enhance productivity using the Vivado HLS tool

  • Describe the high-level synthesis flow

  • Use the Vivado HLS tool for a first project

  • Identify the importance of the test bench

  • Use directives to improve performance and area and select RTL interfaces

  • Identify common coding pitfalls as well as methods for improving code for RTL/hardware

  • Perform system-level integration of IP generated by the Vivado HLS tool

  • Describe how to use OpenCV functions in the Vivado HLS tool

Course Outline

Day 1​

  • Introduction to High-Level Synthesis Overview of the High-level Synthesis (HLS), Vivado HLS tool flow, and the verification advantage.

  • Vivado HLS Tool Flow Explore the basics of high-level synthesis and the Vivado HLS tool.

  • Design Exploration with Directives Explore different optimization techniques that can improve the design performance.

  • Vivado HLS Tool Command Line Interface Describes the Vivado HLS tool flow in command prompt mode.

  • Introduction to HLS UltraFast Design Methodology Introduces the methodology guidelines covered in this course and the HLS UltraFast Design Methodology steps.

  • Introduction to I/O Interfaces Explains interfaces such as block-level and port-level protocols abstracted by the Vivado HLS tool from the C design.

  • Block-Level I/O Protocols Explains the different types of block-level protocols abstracted by the Vivado HLS tool.

  • Port-Level I/O Protocols Describes the port-level interface protocols abstracted by the Vivado HLS tool from the C design.

  • Port-Level I/O Protocols: AXI4 Interfaces Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave), and AXI4-Stream) supported by the Vivado HLS tool.

  • Port-Level I/O Protocols: Memory Interfaces Describes the memory interface port-level protocols (such as block RAM, FIFO) abstracted by the Vivado HLS tool from the C design.

  • Port-Level I/O Protocols: Bus Protocol Explains the bus protocol supported by the Vivado HLS tool. Pipeline for Performance: PIPELINEDescribes the PIPELINE directive for improving the throughput of a design.

Day 2

  • Pipeline for Performance:DATAFLOW Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to executes as soon as possible.

  • Optimizing Structures for Performance Learn the performance limitations caused by arrays in your design. You will also learn some optimization techniques to handle arrays for improving performance.

  • Data Pack and Data Dependencies Learn how to use DATA_PACK and DEPENDENCE directives to overcome the limitations caused by structures and loops in the design.

  • Vivado HLS Tool Default Behavior: Latency Describes the default behavior of the Vivado HLS tool on latency and throughput.

  • Reducing Latency Describes how to optimize the C design to improve latency.

  • Improving Area and Resource Utilization Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization.

  • HLx Design Flow –System Integration Describes the traditional RTL flow versus the Vivado HLx design flow.

  • Vivado HLS Tool C Libraries: Arbitrary Precision Describes the Vivado HLS tool support for the C/C++ languages, as well as arbitrary precision data types.

  • Hardware Modeling Explains hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class.

  • Using Pointers in the Vivado HLS Tool Explains the use of pointers in the design and workarounds for some of the limitations.

 

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