Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users
This course will update experienced ISE® software users to utilize the Vivado® Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.
You will also learn to make path-specific, false path, and min/max timing constraints, as well as learn about timing constraint priority in the Vivado timing engine. Finally, you will lean about the scripting environment of the Vivado Design Suite and how to use the project-based scripting flow.
You will also learn the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.
TechSource Systems is the Sole Distributor and Authorised Training Partner of Mathworks Products
Who Should Attend
Existing Xilinx ISE Design Suite FPGA designers
FPGA design experience
Completion of the Essentials of FPGA Design, Designing for Performance, or Advanced FPGA Implementation courses or equivalent knowledge of Xilinx ISE software implementation tools, techniques, architecture, and FPGA design techniques. Completion of the Vivado Design Suite for ISE Project Navigator Users course is strongly recommended.
Intermediate VHDL or Verilog knowledge
Essential Tcl Scripting for the Vivado Design Suite course
Vivado Design Suite for ISE Software Project Navigator Users course
Vivado System Edition 2016.1
Architecture: UltraScale™ and 7 series FPGAs*
Demo board: None*
After completing this comprehensive training, you will have the necessary skills to:
Access primary objects from the design database and filter lists of objects using properties
Describe setup and hold checks and describe the components of a timing report
Create appropriate input and output delay constraints and describe timing reports that involve input and output paths
Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
Describe all of the options available with the report_timing and report_timing_summary commands
Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
Analyze a timing report to identify how to center the clock in the data eye
Create scripts for the project-based and non-project batch design flows
Describe the UltraFast design methodology checklist
Identify key areas to optimize your design to meet your design goals and performance objectives
Define a properly constrained design
Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
Build resets into your system for optimum reliability and design speed
Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
Identify timing closure techniques using the Vivado Design Suite
Describe how the UltraFast design methodology techniques work effectively through case study/lab experience
1.1 Accessing the Design Database
1.2 Demo: Finding Objects
1.3 Demo: Object Properties
1.4 Demo: Object Connectivity
1.5 Lab 1: Vivado IDE Database
Explore the Vivado IDE database using Tcl commands. Use the Tcl Console to evaluate and enter IOB properties.
1.6 Introduction to Clock Constraints
1.7 Demo: Introduction to Clock Constraints
1.8 Lab 2: Introduction to Clock Constraints
Create complete XDC constraints for the clocking resources in a design. Implement the design and use the available clocking reports to verify results. Understand the first step in the Xilinx baselining recommendation.
1.9 Setup and Hold Timing Analysis
2.0 Generated Clocks
2.1 Demo: Generated Clocks
2.2 I/O Constraints and Virtual Clocks
2.3 Lab 3: I/O Constraints and Virtual Clocks
Create input and output constraints for a source-synchronous design by using the Timing Constraints utility. You will also generate useful timing reports to verify the timing results. Understand the second step in the baselining recommendation.
2.4 Static Timing Analysis and Clocks
2.1 Introduction to Timing Exceptions
2.2 Lab 4: Introduction to Timing Exceptions
Use the Timing Constraints window to enter timing exceptions in the XDC format. You will also generate a useful timing report to verify the timing results. Understand the third and last step in the baselining recommendation.
2.3 Advanced Timing Analysis
2.4 Demo: Introduction to Vivado Timing Reports
2.5 Source-Synchronous I/O Timing
2.6 Lab 5: Source-Synchronous I/O Timing
Make I/O timing constraints for a source-synchronous, double data rate (DDR) interface. Perform a static timing analysis of the interfaces to determine the optimal clock and data relationship for maximum setup and hold-time margin. Finally, adjust the data path delay to realize the optimal timing solution.
2.7 System-Synchronous I/O Timing
2.8 Demo: System-Synchronous I/O Timing
2.9 Scripting in Vivado Design Suite Project Mode
3.0 Lab 6: Scripting in Vivado Design Suite Project Mode
Write Tcl commands in the project-based flow for the design process (from creating a new project through implementation).
3.1 UltraFast Design Methodology Case Study
3.2 Demo: UltraFast Design Methodology Checklist
3.3 UltraFast Design Methodology
3.4 HDL Coding Techniques
3.6 Lab 7: Resets
Investigate the proper design and use of resets. Examine the impact of seeing a design built originally with asynchronous resets, having resets removed, and finally with synchronous resets only used where necessary.
3.8 Lab 8: Inference
Evaluate the implementation results of a design that uses asynchronous resets and infers more dedicated hardware resources when resets are selectively removed from the design. You will also learn how to infer the DSP hardware resources for other common functions required by most FPGA designs.
3.9 Synchronization Circuits
4.0 Demo: Synchronization Circuits
4.2 Demo: Baselining
4.3 Timing Closure and Design Conversion Lab Introduction
4.4 Lab 9: Timing Closure and Design Conversion
Learn how a generic processor design was optimized for the 7 series device architecture with basic design changes that impacted the dedicated hardware usage, design speed, and the device utilization.
4.6 Lab 10: Pipelining
Explore how pipelining can improve performance (increased clock rate and throughput) and facilitate timing closure.
4.7 Register Duplication
4.8 Physical Optimization
4.9 I/O Flip-Flops